Instruction caches are responsible for a high percentage of the chip energy consumption, becoming a critical issue for battery-powered embedded devices. We can potentially reduce the energy consumption of the first level instruction cache (L1-I) by decreasing its size and associativity. However, demanding applications may suffer a dramatic performance degradation, specially in superscalar multi...

Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instruction level parallelism. Unfortunately, naively scaling conventional window designs can significantly degrade clock cycle time, undermining the benefits of increased parallelism. This paper presents a new instruction wind...

This study was an attempt to scrutinize the impact of the Critical Appraisal of Published Research (CAPR) in undergraduate teacher training programs on EFL teachers’ Quantitative Research Literacy (QRL). To meet this objective, 30 male and female ELT teachers were non-randomly selected and randomly assigned to two groups. In two research classes, the experimental group received the CAPR, wherea...

the present study adopts the perspective that metacognitive strategy instruction is bound to occur inside the classroom especially on oral tasks. accordingly, the researchers investigated whether metacognitive strategy instruction prior to oral tasks was more successful than conventional ways in improving efl learners’ oral proficiency. to this end, 56 participants studying in a language school...