The access control on data is normally on per page basis and is implemented in the Translation Lookaside Buffer (TLB) via page tables managed by memory management of operating systems. To optimize the memory reference performance, operating systems specify if a page of data should be encached or not, so that unnecessary and undesirable data encaching will be avoided. It is also desirable to be ...

Stack-processors, which abandon register files and instead work directly on the stack content have recently enjoyed a resurgence of interest in conjunction with higher level languages. However, the way in which local variables are handled by typically stack-targeted compilers leaves much room for improvement. These issues are not restricted to stack architectures using a C-compiler, although th...

We describe a new result that shows that representing a matrix A as a collection of square blocks will reduce the amount of data reformating required by dense linear algebra factorization algorithms from O(n) to O(n). 1 Description of a Fortran and C Inefficiency for Dense Linear Agebra Factorizations The current Most Commonly Used (MCU) Dense Linear Algebra (DLA) algorithms for serial and SMP ...

IBM introduced Power4-based systems in 2001. The Power4 design integrates two processor cores on a single chip, a shared second-level cache, a directory for an off-chip third-level cache, and the necessary circuitry to connect it to other Power4 chips to form a system. The dual-processor chip provides natural thread-level parallelism at the chip level. Additionally, the Power4’s out-of-order ex...

The increasing complexity of deep learning systems has pushed conventional computing technologies to their limits. While the memristor is one prevailing for acceleration, it only suited classical layers where two operands, namely weights and inputs, are processed simultaneously. Meanwhile, improve computational efficiency emerging applications, a variety non-traditional requiring concurrent pro...

The problem of multiprocessor scheduling can be stated as finding a schedule for a general program graph to be executed on a multiprocessor system so that the schedule length can be minimised. This scheduling problem is known to be NP-hard and heuristic algorithms have been proposed to obtain optimal and sub optimal solutions. Almost all coarse grained program graph nodes don’t need all of thei...

The memristor is promising to be the basic cell of next-generation computation systems. Compared to the traditional MOSFET device, the memristor is efficient over energy and area. But one of the biggest challenges faced with researchers is how to program a memristor’s resistance precisely. Recently, an algorithm designed to save 8 valid bits in each memristor is proposed, but this is still not ...

so we are able to obtain a direct access to the field which our instructor works on; the second is that it focuses more on mathematical theory and simulation of the process of designing, something that the previous papers about the concept of database rarely mention. I learn much from reading this paper, including the algebraic theory, technique for simulation, and the application of the method...

This paper 1 introduces analogical and deductive methodologies for the design medical processor units (MPUs). From the study of evolution of numerous earlier processors, we derive the basis for the architecture of MPUs. These specialized processors perform unique medical functions encoded as medical operational codes (mopcs). From a pragmatic perspective, MPUs function very close to CPUs. Both ...