This article provides an illustration of the design process for 5-2 and 7-2 compressors operating at extremely high speeds. When compared to prior designs, new approach significantly reduced gate-level delay while maintaining appropriate overall transistor gate count. With help 7:2 5:2 compressor infusion, when earlier latency has been decreased counts have remained within acceptable bounds. Th...

A new FFT architecture for real-valued signal is proposed using Radix-2 algorithm. It is based on modifying flow graph of the FFT algorithm such that it has both real and complex datapaths. A redundant operation in flow graph is replaced by imaginary part. Using folding technique RFFT architecture with any level of parallelism can be achieved. This RFFT architecture will lead to low hardware co...

Digital Signal Processing (DSP) often involves multiplications with a set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error, our approach scales the original coefficients to enable the partitioning of each multiplication into a coll...

Digital Signal Processing (DSP) often involves multiplications with a fixed set of coefficients. This paper presents a novel multiplier design methodology for performing these coefficient multiplications with very low power dissipation. Given bounds on the throughput and the quantization error of the computation, our approach scales the original coefficients to enable the partitioning of each m...

The Wallace Multiplier is mainly used in the Arithmetic & Logic Unit (ALU) to perform the scientific computation in processors, controller etc... The existing multiplication technique like booth multiplier, array multiplier etc requires more time in multiplications. Hence Wallace Multiplier has been designed by using the parallel process to reduce the delay. The regular Wallace Multiplier requi...

Representing finite field elements with respect to the polynomial (or standard) basis, we consider a bit parallel multiplier architecture for the finite field GF (2). Time and space complexities of such a multiplier heavily depend on the field defining irreducible polynomials. Based on a number of important classes of irreducible polynomials, we give exact complexity analyses of the multiplier ...

We present a Matrix-vector form of Karatsuba multiplication over GF (2m) generated by an irreducible trinomial. Based on shifted polynomial basis (SPB), two Mastrovito matrices for different Karatsuba multiplication parts are studied. Then related multiplier architecture is proposed. This design effectively exploits the overlapped entries of the Mastrovito matrices to reduce the space complexit...

The multiplier is the building block required in the adaptive equalizer that is most costly in terms of both speed and power. Since the power consumed by a CMOS digital circuit is CV 2 f, reducing the power supply and employing one or a combination of parallelism and pipelining can result in a significant power savings [4]. Applications using a power supply of 3.3 V are becoming widespread in o...

This paper describes implementation of radix-4 Modified Booth Multiplier and this implementation is compared with Radix-2 Booth Multiplier. Modified Booth’s algorithm employs both addition and subtraction and also treats positive and negative operands uniformly. No special actions are required for negative numbers. In this Paper, we investigate the method of implementing the Parallel MAC with t...