This paper analyze the soft error tolerance related to layout structures on 65-nm bulk and SOI processes. The layout structure in which well contacts are placed between redundant latches suppresses MCU effectively. Also the tolerance of SOI structure transistor is estimated by TCAD simulations. The charge collection mechanism is suppressed by the BOX (Buried Oxide) in SOI transistor. Charge sha...

This paper introduces a novel silicon-on-insulator (SOI) metal–semiconductor field-effect transistor (MESFET) with an implanted N layer (INL-SOI MESFET) to improve the DC and radio frequency characteristics. The DC and radio frequency characteristics of the proposed structure are analyzed by the 2-D ATLAS simulator and compared with a conventional SOI MESFET (C-SOI MESFET). The simulated result...

We report on a novel 3D integration technology suitable for stacked CMOS image sensors by using high-density Au electrodes embedded within every pixel for vertical interconnection between silicon-on-insulator (SOI) layers. Unlike the conventional technique based on the through silicon vias (TSVs) or microbumps, the presented process is suitable for ultra-high-density 3D integration within an im...

The fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation is the first model for circuit simulation based on a complete surface-potential description. HiSIM-SOI solves the surface potentials at all three SOI-surfaces perpendicular to the channel surface self-consistently. Besides verification against measured I-V characteristics, HiSIM-SOI is also verified with a 1/f noise analysis, ...

Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BC-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 m with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) ...

The silicon-on-insulator (SOI) material system is today widely recognized as one of the most important platforms for the development of photonic components. This is mainly due to the fact that the mass fabrication techniques of the CMOS technology can be used for the fabrication of these SOI components. However, using silicon for photonic components has significant downsides. For example, it is...

Smart power ICs, which monolithically integrate low-loss power devices and control circuitry, have attracted much attention in a wide variety of applications [1], [2]. Commonly used smart power devices are the LDMOS and LIGBT implemented in bulk silicon or SOI (Silicon on Insulator). One of the key issues in the realization of such ‘smart power’ technology is the isolation of power devices and ...

In this paper an introduction to substrate noise in silicon on insulator (SOI) is given. Differences between substrate noise coupling in conventional bulk CMOS and SOI CMOS are discussed and analyzed by simulations. The efficiency of common substrate noise reduction methods are also analyzed. Simulation results show that the advantage of the substrate isolation in SOI is only valid up to a freq...

Double-gate fully depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits. This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance. We study how the added back-gate capacitance affects circuit power and performance; how to tradeoff the enhanced short-channel effect immunity with the added bac...

Introduction An excess of the drain current ID, related to the floating body effect and hole generation by impact ionization, can appear in the saturation region of SOI MOSFETs [1]. This mechanism has been reported for drain voltages below the band-gap voltage (VD=0.7 V) by including additional energy gain mechanisms to overcome the thresholds of impact ionization processes [2,3]. In this paper...