This paper demonstrates how the PIXAPP Photonics Packaging Pilot Line uses its extensive packaging capabilities across European partner network to design and assemble a highly integrated silicon photonic-based optical transceiver. The processes used are based on PIXAPP's open access rules or Assembly Design Kit (ADK). transceiver was designed have Tx Rx elements single photonic chip, tog...

We propose 3D mesh-based optical network-onchip (ONoC) based on a novel low-cost 6x6 optical router, and quantitatively analyze thermal effects on the 3D ONoC. Evaluation results show that with the traditional thermal tuning technique using microheater, the average power efficiency of the 3D ONoC is about 2.7pJ/bit, while chip temperature varies spatially between 55C and 85C. In comparison, a n...

As the computational performance of microprocessors continues to grow through the integration of an increasing number of processing cores on a single die, the interconnectionnetwork has become the central subsystem for providing the communications infrastructure among the on-chip cores as well as to offchip memory. Silicon nanophotonics as an interconnect technology offers several promising ben...

Systems-on-Chip architecture integrates several heterogeneous components on a single chip. A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead. Network-on-chip (NoC) is a new approach for communication infrastructure of Systems-on-Chip (SoC) design, which provides network based solution for on-chip communication....

Xiang Zhang and Ahmed Louri Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721 E-mail:{ zxkidd, louri}@ece.arizona.edu Abstract: We explore silicon photonics and 3D stacked technology to implement a photonic network-on-chips. The proposed scheme provides 2.56 Tb/sec bandwidth with a much reduced power consumption and latency compared to any leading on-chip photonic net...

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today’s NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power co...

Heat balance is of critical importance on the design of network-on-chip (NoC). In a 3D topology NoC, routing algorithm should take considerations of each layer’s peak temperature and traffic to prolong chip’s service life. In this paper, we propose a heat-balanced, deadlock-free routing algorithm named Direct Ratio Transport Layer (DRTL). DRTL distributes and arranges traffics according to the ...

To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and ca...

Network-on-Chip (NoC) has recently emerged as an efficient communication solution for the System-on-Chip (SoC) design. Design space exploration and performance evaluation are the most essential task in NoC design. In this paper, an ABC based design space exploration framework for the NoC design is proposed. The objective of the design space exploration is to minimize the total energy consumptio...

In this paper, we propose a new packing strategy to find a free resource for run-time mapping of application tasks to NoC-based Heterogeneous MPSoC. The proposed strategy minimizes the task mapping time in addition to placing the communicating tasks close to each other. To evaluate our approach, a comparative study is carried out for a platform containing single task supported PEs. Experiments ...