نتایج جستجو برای: pipelining
تعداد نتایج: 1926 فیلتر نتایج به سال:
In order to speed up convolutional neural networks (CNNs), this study gives a complete overview of the use FPGA-based pipelining for hardware acceleration CNNs. These days, most people (CNNs) perform computer vision tasks like picture categorization and object recognition. The processing memory demands CNNs, however, can be excessive, especially real-time applications. has emerged as viable opt...
Modulo scheduling is the premier technique for throughput maximization of loops in high-level synthesis by interleaving consecutive loop iterations. The number clock cycles between data insertions called initiation interval (II). For maximization, this value should be as low possible; therefore its minimization main optimization goal. Despite long historical existence, modulo always remained a ...
High performance processors based on pipeline processing play an important role in scientific computation. We have proposed a hybrid pipeline architecture named Jetpipeline in our former work. The concept of Jetpipeline comes from the integration of superscalar, VLIW and vector architectures. Jetpipeline has multiple instruction pipelines, which execute multiple instructions like superscalar ar...
Wave pipelining improves the throughput of a circuit by exploiting the delays of combinational elements, rather than register clocks, for synchronization. Our proposed approach, called HyPipe, combines conventional register-based pipelining with wave pipelining and aims to take advantage of both pipelining methods [5]. In this paper, we applied HyPipe to develop 4-bit signed multipliers and 4-b...
HTTP response size is a well-known side channel attack. With the deployment of HTTP/2.0, response size attacks are generally dismissed with the argument that pipelining and response multiplexing prevent eavesdroppers from finding out response sizes. Yet the extent to which pipelining and response multiplexing actually hide HTTP response sizes has not been adequately investigated. In this paper ...
In nanometer scale integrated circuits, concurrent insertion of repeaters and sequential elements into the global interconnect lines has been proposed to support multicycle communication—a concept known as interconnect pipelining. The design targets of an interconnect-pipelining scheme are to ensure high reliability, low-power consumption, and less delay cycles. This paper presents an in-depth ...
The performance of a Java Virtual Machine (JVM) interpreter running on a very long instruction word (VLIW) processor can be improved by means of pipelining. While one bytecode is in its execute stage, the next bytecode is in its decode stage, and the next bytecode is in its fetch stage. The paper describes how we implemented threading and pipelining by rewriting the source code of the interpret...
We address the problem of time optimal software pipelining of loops with control ows, one of the most di cult open problems in the area of parallelizing compilers. We present a necessary condition for loops with control ows to have equivalent time optimal programs, generalizing the result by Schwiegelshohn et al., which has been the most signi cant theoretical result on the problem. As part of ...
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