The need to support various digital signal processing (DSP)and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. Hence, improving the energy efficiency of multiplications is critical. In this brief, we propose multi...

In this paper, for nonconvex optimization problem with both equality and inequality constrains, we introduce a new augmented Lagrangian function and propose the corresponding multiplier algorithm. The global convergence is established without requiring the boundedness of multiplier sequences. In particular, if the algorithm terminates in finite steps, then we obtain a KKT point of the primal pr...

In this paper, a double balanced radio frequency multiplier is presented which is customized for transmitted reference ultra wideband (UWB) receivers. The multiplier uses 90nm model parameters and exploits compensating transistors to provide controllable gain for a Gilbert core. After performing periodic and quasiperiodic non linear analyses the RF mixer (multiplier) achieves a voltage conversi...

In the Fictitious Domain Method with Lagrange multiplier (FDM) the physical domain is embedded into a simpler but larger domain called the fictitious domain. The partial differential equation is extended to the fictitious domain using a Lagrange multiplier to enforce the prescribed boundary conditions on the physical domain while all the other data are extended to the fictitious domain. This le...

This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural models were designed to implement the 53-bit mantissa path of the IEEE standard 754 for floating point multiplication, and tested for functionality in Verilog. The design, which was done in dual-rail domino, was simulated ...

Bit-sequential multiplier is being studied in a (+1, -1) binary representation. The maximum length of multiplier for a fix point numbers consists of n module. Each module is a five bit adder which contains 5 inputs and 3 outputs. It also contains an additional pin at the input as well as at the output. Computation time for multiplication is of the order of O(n). Hardware realization of module i...

The IEEE-754 standard floating point multiplier that provides highly precise computations to achieve high throughput and low area on the IC have been improved by insertion of pipelining technique. Floating point multiplier-using pipelining has been simulated, analyzed and its superiority over traditional designs is discussed. To achieve pipelining, one must subdivide the input process into sequ...

The Floating Point in two-term Dot-Product of multiplier referred as discrete design. Floating Point is a wide variety for increasing accuracy, high speed, high performance and reducing delay, area and power consumption. This application of floating point is used for algorithms of Digital Signal Processing and Graphics. Many floating point application is to reduce area, from the survey the fuse...

This article deals with the VLSI architecture of the Floating point and Galois field multiplier, using a technique called Wave-pipelining. Wave -pipelining is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than conventional pipelining techniques. Wave pipelining can improve the throughput of a logic circuit while avoiding some of the overheads o...

Asymptotic reductions of the Fanno model for one-dimensional turbulent compressible flow of a perfect gas in a long tube are investigated. Conservation laws are derived using the multiplier method for a nonlinear wave equation and a nonlinear diffusion equation for the mean velocity and a nonlinear diffusion equation for the mean pressure. Two conserved quantities for the mean velocity are obta...