A low-voltage, low-power four-quadrant analog multiplier with optimized current-efficiency is presented. Its core corresponds to a pseudodifferential cascode, gain-boosting triodetransconductor. According to a low-voltage 1.2μm CMOS n-well process, operand differential-amplitudes are 1.0Vpp and 0.32Vpp for a 1.3V-supply. Common-mode voltages are properly chosen to maximize current-efficiency to...

TOBUREN, MARK CHRISTOPHER. Power Analysis and Instruction Scheduling for Reduced di/dt in the Execution Core of High-Performance Microprocessors. (Under the direction of Dr. Thomas M. Conte.) Power dissipation is becoming a rst-order design issue in high-performance microprocessors as clock speeds and transistor densities continue to increase. As power dissipation levels rise, the cooling and r...

System on chip (SOC) design integrates many complex modules in one chip. As number of modules per chip is increasing, number of transistors in a chip increases resulting in increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed if the basic building blocks of the circuit are designed for lower power dissipation and occupy less space. Flip-F...

TOBUREN, MARK CHRISTOPHER. Power Analysis and Instruction Scheduling for Reduced di/dt in the Execution Core of High-Performance Microprocessors. (Under the direction of Dr. Thomas M. Conte.) Power dissipation is becoming a rst-order design issue in high-performance microprocessors as clock speeds and transistor densities continue to increase. As power dissipation levels rise, the cooling and r...

The Power Factor Approximation (PFA) power estimation method is reviewed and applied to VLSI array processing systems. The power dissipation of 1, 2, and 3 dimensional algorithms implemented on linear, hexagonal, and cubic processor arrays is investigated. Closed form equations are developed which show how the overall power dissipation is influenced by an algorithm's size and dimensionality, th...

The importance of low-power design is not just critical to portable devices but also to line powered equipment like TV products. Power dissipation strongly influences the price of the chip, since the packaging and cooling costs increase dramatically with increasing power dissipation. In this paper, we analyse architectures that enable the design of a low-power picture-rate up-conversion module,...

As the number of applications for embedded and real-time systems has grown, running systems at a lower power dissipation level has become an important issue, especially for the battery-based systems. Past studies have shown that the cache is responsible for a large part of the power dissipation in a system chip. Thus, reducing the power dissipation in the cache has become an important research ...

Power dissipation and energy consumption have recently become first-order design constraints for microprocessors. In this paper we present the measured power dissipation of several SPEC benchmarks executing on a Pentium 4 processor. Using on-chip performance monitoring counters, we dynamically correlate relevant performance metrics such as instructions per cycle, second-level cache hits, and bo...

|Gate-sizing is an eeective technique to optimize CMOS circuits for dynamic power dissipation and performance while dual-V th (threshold voltage) CMOS is ideal for leakage power reduction in low voltage circuits. This paper focuses on simultaneous dual-V th assignment and gate-sizing to minimize the total power dissipation while maintaining high performance. An accurate power dissipation model ...