Floating-point matrix multiplication is arguably the most important kernel routine in many scientific applications. Therefore, its efficient implementation is crucial for the overall performance of any computer system targeting scientific computations. In this paper, we propose a holistic solution to accelerate matrix multiplication on reconfigurable hardware using the MOLEN polymorphic process...

This paper presents a novel methodology for instruction set customization of RISPs (Reconfigurable Instruction Set Processors) using morphable structures. A morphable structure consists of a group of hardware operators chained together to implement a restricted set of custom instructions. These structures are implemented on the reconfigurable fabric, and the operators are enabled/disabled on de...

Extensible processors allow customization for an application by extending the core instruction set architecture. Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit. Custom instructions (CIs) usually are extracted from critical portions of applications. This paper presents approaches fo...

In this invited talk, we characterize the approaches taken to form customized processors using combinations of programmable processors and Field Programmable Gate Arrays (FPGAs). We investigate these approaches by considering how and where customization takes place. We consider approaches to customize within a processors ISA, and external to the ISA. We also consider how processor customization...

Applications such as mobile devices (cellular phones, PDA, consumer electronics) does require both a very powerful processor(s) as well as low power consumption because of the limited power supply on such a device (batteries). Saving power can be achieved on three different levels. Firs, it could be achieved through low power VLSI technology where the transistors consume less power for switchin...

To my father and all other members of my family Summary In this dissertation, we propose to combine programmability with reconfig-urability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor organization can be adapted to the specific requi...

This paper introduces the mapping of MPEG video decoders on ADRES, IMEC’s new coarse-grain reconfigurable and fully C-programmable array processor that targets nomadic devices. ADRES is a flexible template that allows the instantiation of many different processor versions. An XML-based architecture description language allows a designer to easily generate different processor instances with full...

This paper presents the overall structure of PAPIA2, a pyramid system belonging to the family of massive parallel machines. It embeds the topology of the quad-pyramid into a highly regular, fault tolerant, eight-connected processor array by means of specially reconfigurable near-neighbor interconnections. The system comes with a fully-fledged software environment designed to optimize the use of...

The ReRISC processor gives users the opportunity to create application specific instructions for enhanced performance while providing the programming convenience of a conventional RISC processor. The core of the ReRISC consists of an array of 38x8 computational elements, each with 8 configuration contexts that are selectable on a cycle by cycle basis. The computational elements default to the M...