Register files (RF) are known to consume about 20% of the power inside a processor. Embedded systems, due to area and timing constraints, generally have small register files, which can cause significant register pressure. This work explores how having a map-table or a map-vector can decrease the power dissipation in the processor. The distribution of register writes and sharing of commonly occu...

In this paper, we present a new pseudo-random sequence generator, constructed by the generalized discrete Baker transformation. This new generator is called Cascaded Baker Register Machine (CBRM), which uses the sensitivity of chaotic behaviour and allows the application of automataand shift-register theory. It is shown that a CBRM has good properties of randomness, such as large periods and hi...

The above paper rVA] has the following error in the CStruldbrugg' algorithm (the main bounded tag algorithm). In the following, we assume familiarity with the paper. The "selection rule" of the reader is not sufficient to guarantee atomicity, but only the weaker regularity condition. Informally, regularity for multiwriter registers means that a reader does return a value written by a write, suc...

Let s = (s 1 ; s 2 ; : : : ; s n) be a sequence of characters where s i 2 Z p for 1 i n. One measure of the complexity of the sequence s is the length of the shortest feedback shift register that will generate s, which is known as the maximum order complexity of s 17, 18]. We provide a proof that the expected length of the shortest feedback register to generate a sequence of length n is less th...

In the process of compiling a computer programme, we consider the problem of allocating variables to registers within a loop. It can be formulated as a coloring problem in a circular arc graph (intersection graph of a family F of intervals on a circle). We consider the meeting graph of F introduced by Eisenbeis, Lelait and Marmol. Proceedings of the Fifth Workshop on Compilers for Parallel Comp...

ÐIn this paper, we examine the effectiveness of a new hardware mechanism, called Register Queues (RQs), which effectively decouples the architected register space from the physical registers. Using RQs, the compiler can allocate physical registers to store live values in the software pipelined loop while minimizing the pressure placed on architected registers. We show that decoupling the archit...

In testing certain systems, checking for burst errors is important. This is due to the fact that errors are confined to a certain number of bits. If signature analysis is used to test a circuit then the testing capabilities depend on the polynomial that defines the linear feedback shift register (LFSR) used in the test. In this paper we show that the LFSR that is suitable for checking for burst...

Register files account for a significant fraction of the power dissipation in modern RISC processors. Register file banking is an effective alternative to monolithic register files in embedded systems. We propose a profile-based technique to arrive at a customized energy-efficient bank configuration for a given application on a dual bank register file. The technique consists of a register renam...

Using the structure of Singer cycles in general linear groups, we prove that a conjecture of Zeng, Han and He (2007) holds in the affirmative in a special case, and outline a plausible approach to prove it in the general case. This conjecture is about the number of primitive σ-LFSRs of a given order over a finite field, and it generalizes a known formula for the number of primitive LFSRs, which...

This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation of this Systolic Shared Register architecture; a working 470-processor prototype system performs 108 MOPS. A 32-chip, 1504-processor implementation could provide 5 GOPS of systolic co-processing power on a single board.