This paper presents the design and analysis of a 5.5 V Class-D stage used in two fully integrated watt-level, +32.0 dBm and +29.7 dBm, outphasing RF Power Amplifiers (PA) in standard 130 nm and 65 nm CMOS technologies. The Class-D stage utilizes a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V technologies without excessive device vol...

A two-stage CMOS operational amplifier with both, gain-boosting and indirect current feedback frequency compensation performed by means of regulated cascode amplifiers, is presented. By using quasi-floating-gate transistors (QFGT) the supply requirements, the number of capacitors and the size of the compensation capacitors respect to other Miller schemes are reduced. A prototype was fabricated ...

The current mirrors are one of the most important circuits in designing the analog and mixed-mode circuit. A low power and low voltage high-performance CMOS current mirror with optimized input and output resistance are presented in this paper. SPICE simulations confirm the high-performance CMOS current mirror with power supply close to the threshold voltage of the transistor. In this paper, for...

In this paper, a 10-Gb/s inductorless CMOS receiver front end is presented, including a transimpedance amplifier and a limiting amplifier. The transimpedance amplifier incorporates Regulated Cascode (RGC), active-inductor peaking, and intersecting active feedback circuits to achieve a transimpedance gain of 56 dB and a bandwidth of 8.27 GHz with a power dissipation of 35 mW. The limiting amplif...

This paper presents a simple behavioral model with experimentally extracted parameters for packaged cascode gallium nitride (GaN) field-effect transistors (FETs). This study combined a level-1 metal–oxide–semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), and a diode model to simulate a cascode GaN FET, in which a JFET was used to simulate a metal-insulat...

A current mirror (CM) based on self cascode MOSFETs low voltage analog and mixed mode structures has been proposed. The proposed CM has high output impedance and can operate at 0.5 V. P-Spice simulations confirm the high performance of this CM with a bandwidth of 6.0 GHz at input current of 100 μA. Keywords—Current Mirrors, Composite Cascode Structure, Current Source/Sink.

We present an area-efficient and low-power four-channel 25-Gb/s trans-impedance amplifier for Rx analog front-end (Rx-AFE) on optical receiver. The proposed circuit features a local negative-feedback (TIA) to expand the bandwidth. TIA post-amplifier use regulated cascode (RGC) topology two differential stages with inductive peaking bandwidth extension technique acquire 19.6 GHz of -3 dB 53.3 dB...

In this paper we report the fabrication, design and testing of an uncooled infrared imager based on an active pixel heat balancing technique. The imager is fabricated using a commercial CMOS process plus a simple electrochemical etch stop releasing step. The basic active pixel detector structure consists of a simple cascode CMOS amplifier in which the PMOS devices are built inside a thermally-i...

This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. Using 0.35μm CMOS process, the designed folded cascode OTA achieves a DC gain of 77.5dB and a unity...

The demonstration of a 75-305-GHz power amplifier (PA) monolithic microwave integrated circuit (MMIC) is presented in this letter. PA based on an eight-cell traveling-wave unit (UA). Each cell contains RF cascode with two two-finger transistors gate width 20 ?m each. In the output stage, balanced configuration combines UAs Lange couplers. front, third UA used as driver amplifier. MMIC fabricate...