A testing system has been designed to detect the single event upset failure of SRAM chips in this paper: a visual test bench for failure monitoring is developed based on LabVIEW, it could perform the task of data acquisition, storage and results analysis. At the testing board, the test vectors based on March Calgorithm are written to the reference SRAM and the under-test SRAM through FPGA. NI H...

Optical data transmission has been chosen for the ATLAS Pixel and SemiConductor Tracker to deliver both timing and control information to the detector modules and transmit tracking data to the remote computer room. Radiation hardness of individuals optical components and their ASICs drivers have been reported in previous papers. We will report here the Single Event Upset studies carried out on ...

Abstract In high-energy physics experiments, it is a trend to implement digitalization in the front end of readout electronics based on Application Specific Integrated Circuits (ASICs), which are exposed radiation environment. As an important part ASIC, SRAM (Static Random-Access Memory) impressionable Single Event Upset (SEU) due Therefore, new SEU-tolerant cell structure was designed our prev...

The instruction decoder is one of the most complex and least regular logic structures in a modern processor that attempts to process multiple variable-length CISC instructions per cycle. This structure consumes a significant amount of area and is heavily utilized, making it vulnerable to logic soft errors. This paper analyzes a parallel decoder using gate-level modeling and statistical fault in...

We have designed and fabricated a compact array-based optical engine for transmitting data at 10 Gb/s. The device consists of a 4-channel ASIC driving a VCSEL (Vertical Cavity Surface Emitting Laser) array in an optical package. The ASIC is designed using only core transistors in a 65 nm CMOS process to enhance the radiation-hardness. The ASIC contains an 8-bit DAC to control the bias and modul...

The Soft Error Rate (SER) is expressed as Failure-in-Time (FIT) units, defined as one soft error occurrence every billion hours of operation.Often SEUmitigation is not required because of the low chance of occurrence. However, for highly complex systems, such as with multiple high-density components, error rate may be a significant system design factor. If your system includes multiple FPGAS an...

Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by sin...

As CMOS technology down sized into double digit nanometer ranges, variations are a serious concern due to uncertainty in devices and interconnect characteristics. The single event upset (SEU) is changing the state of a memory cell due to the strike of an energetic particle. The single event multiple effects are likely to increase in nanometer CMOS technology due to reduced device size and scali...

This paper describes a soft-error tolerant and marginenhanced nMOS-pMOS reversed 6T SRAM cell. The 6T SRAM bitcell comprises pMOS access and driver transistors, and nMOS load transistors. Therefore, the nMOS and pMOS masks are reversed in comparison with those of a conventional bitcell. In scaled process technology, The pMOS transistors present advantages of small random dopant fluctuation, str...

Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked element is developed with multiple thresholds, regular architecture, increased number single-event upset (SEU)-insensi...