We present two novel circuit design techniques that effectively reduce the impact of radiation-induced single event transients (SET) on logic circuits. Both techniques can be applied to large CMOS designs and have been verified by a recently developed soft error rate analysis (SERA) methodology [3]. Rapid scaling of integrated circuit process technology has resulted in significant improvements ...

A method is proposed for making asynchronous (QDI) circuits entirely tolerant to soft errors caused by radiation or other noise effects. The method has three components: (1) a special kind of duplication for random logic, (2) special circuitry for arbiter and synchronizer (as needed for example for external interrupts), and (3) error correction for memory arrays. An entire microcontroller has b...

With shrinking device size and increasing complexity, soft errors are becoming an issue in the reliability of digital systems. To make efficient robust systems, it is important to understand how soft errors affect the quality of output for the target applications. Probabilistic inference applications are interesting since they produce non-exact results and yet are useful in many different field...

The topic of this thesis is about soft-errors in digital systems. Different aspects of soft-errors have been addressed here, including an accurate simulation model to emulate soft-errors in a gate-level net list, a simulation framework to study the impact of soft-errors in a VHDL design and an efficient architecture to minimize the impact of soft-errors in a DSP processor. The first two chapter...

The trend of continuing technology scaling in circuits exaggerates effects of physical phenomena, such as particle strikes [1] and process variation [2], that cause soft errors . While recent advances in fabrication technology decrease the severity of these effects for the next transistor generation [3] [4], the trend of the increasing error rates inevitably continues with further scaling or ch...

INTRODUCTION For technology scaling beyond 20 nm, FinFET transistors will replace the conventional planar geometry. The driving force for the introduction of FinFET architecture is the superior immunity to short-channel effects and the reduction of the effects of process variation on device performance exhibited by the FinFET.[1-4] Figure 1 shows a comparison of architectures of the planar FET ...

Over the last years, an increasing number of safety-critical tasks have been demanded to computer systems. In this paper, a software-based approach for developing safety-critical applications is analyzed. The technique is based on the introduction of additional executable assertions to check the correct execution of the program control flow. By applying the proposed technique, several benchmark...