Silicon-on-insulator MESFETs have been fabricated using standard CMOS process flows and their characteristics have been measured over a temperature range of –180°C to + 300°C. From the measured data a TOM3 Spice model has been extracted. The Spice model has been used to simulate a two-stage operational transconductance amplifier and a voltage controlled oscillator. The circuit simulations show ...

Three standard 1/f noise models for MOSFETs are actually implemented in software packages: SPICE, HSPICE and recently BSIM3v3 noise model. The aim of this contribution is to show the limitation for each of these implementations by comparing noise simulations to noise measurement data. We demonstrated that 1/f noise model implemented in SPICE and HSPICE can not predict correctly noise in all ope...

For SPICE level circuit development, corner models address the designer’s need for fast simulations which can reproduce specific scenarios of interest. To systematically and automatically determine the model parameters for the corners, we present a methodology based on a constrained least squares optimization. We also show how it performs when applied to some of our devices for best and worst c...

On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped model. The waveform describing the SSN voltage is quite close to the waveform obtained from SPICE. The peak value of the simultaneo...

In this paper, an analytical model for a vertical double implanted metal-oxide semiconductor (DIMOS) transistor structure in 4H-Silicon Carbide (SiC) is presented. Simulation for transport characteristics of the SiC MOSFET with the exact device geometry is carried out using the commercial device simulator MEDICI. A rigorous experimental testing and characterization is done on a 4H-SiC DIMOS tra...

The multi-level methodology for CMOS SOI/SOS IC element parameterization for VLSI radiation hardness prediction by CAD systems is developed. The methodology includes semiconductor technology simulation, CMOS SOI/SOS MOSFET device simulation with radiation effects, irradiated test structures investigation, radiation dependent SPICE model parameter extraction with ICCAP. The measured data of irra...