This paper presents the design of a multilevel pyramidically wound symmetric (MPS) inductor structure. Being multilevel, the MPS inductor achieves high inductance to area ratio and hence occupies smaller silicon area. The symmetric inductor is realized by winding the metal trace of the spiral coil down and up in a pyramidal manner exploiting the multilevel VLSI interconnects technology. Closed ...

In this paper, deep sub-micron CMOS process compatible high Q on chip spiral inductors with air gap structure were designed and fabricated. In the design the electromagnetic solver, SONNET, and the finite element program, ANSYS, were used for electrical-characteristics and maximum mechanical strength, respectively. The copper wires were capped with electroless Ni plating to prevent the copper f...

The design and characterization process of a package-embedded spiral inductor is investigated in this paper via comprehensive electromagnetic simulations. A realistic, multi-layer flip-chip package is considered and modeled in a commercial, full wave electromagnetic simulator. At constant package area, parasitic resistance of a given inductance is minimized. The applicability of the proposed pa...

On-chip circular vertical solenoid inductors have been designed and fabricated using standard 6-metal layer CMOS process. Compared to the 4.1nH circular planar spiral inductor on the same chip, the 4.8nH solenoid inductor gives about 20% increase in maximum quality-factor (QF) and 50% increase in self-resonant frequency (SRF), but only occupies 20% of the area. The inductor impedance can be mod...

This paper presents a 1.2 GHz continuous time 6 order band-pass Sigma Delta Analog to Digital modulator in IBM 0.18 um CMOS technology. Traditional RLC circuits, with spiral inductors as resonators, were replaced with active inductor based resonators with negative impedance circuits to enhance the quality factor, reduce chip area and eliminate post processing needs. Simulink and Cadence simulat...

An original parameters extraction strategy has been developed using a physical and scalable 2π equivalent on-chip spiral inductors RLC circuit model. This strategy based on optimization only, was used to model spice model parameters as a function of geometrical inductor parameters. The data used in this paper were obtained by using a 3D electromagnetic Field Solver combined with a Design of Exp...

Different methods to build integrated resonators and frequency tuning elements are reviewed. Two new figures of merit are defined and used to compare voltage-controlled oscillators (VCO) reported by various authors. It is shown that bipolar and CMOS VCOs can achieve similar performances. Introduction A large number of integrated resonator-based oscillators have been reported during the last few...

On-chip spiral micromachined inductors fabricated in a 0.18m digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factor...