This article proposes a disruptive device concept which meets both low power and high performance criterion for post-CMOS computing and at the same time enables aggressive channel length scaling. This device, hereafter refer to as two-dimensional electrostrictive field effect transistor or 2D-EFET, allows sub-60 mV/decade subthreshold swing and considerably higher ON current compared to any sta...

Black phosphorus (BP) has emerged as a promising two-dimensional (2D) material for next generation transistor applications due to its superior carrier transport properties. Among other issues, achieving reduced subthreshold swing and enhanced hole mobility simultaneously remains a challenge which requires careful optimization of the BP/gate oxide interface. Here, we report the realization of hi...

Lowering both the threshold voltage (Vth) and subthreshold swing (S) at the same time is essentially required for O.1pm and below O.lym MOSFETs with low supply voltage. In this paper, we discuss a temperature scaling concept of MOSFET and the device characteristics of the fabricated 77K MOSFETs. In the temperature scaling concept, the physical quantities relating to potential are scaled with op...

It is my great pleasure to announce the winner of 2020 Electron Devices Society George E. Smith Award given a paper published in IEEE Device Letters 2020. The selection was made by vote EDL’s Editors. letter titled “Theoretical Limit Low Temperature Subthreshold Swing Field-Effect Transistors” and it authored Arnout Beckers, Farzan Jazaeri, Christian Enz, all with Integrated Circuits Laboratory...

The subthreshold swing (SS) of MOSFETs decreases with temperature and then saturates below a critical temperature. Hopping conduction via the band tail has been proposed as possible cause for SS saturation. On other hand, numerical simulations have shown source-to-drain tunneling (SDT) current limits at low temperatures. It argued which transport mechanism dominates cryogenic current. Hence, fi...

The potential to perform at low voltages is a unique feature of carbon nanotube thin-film transistors (CNT-TFTs) when compared to more common TFT material options, such as amorphous Si or organic films. In this work, CNT-TFTs are fabricated using high-purity CNTs (verified electrically to be !99% semiconducting) on an embedded gate device structure, which allows for scaling of the dielectric (e...

--In today’s technological environment, there is a huge demand for devices with low power and low cost storage space. Memories with low power are driving the entire VLSI industry as most of the devices work on remote power supply. Demand of low power becomes the key of VLSI designs rather than high speed, particularly in embedded SRAM’s and caches. The tunneling field effect transistor uses the...

We present results on small-molecule pand n-type organic semiconductors in combination with the highly water repellent fluoropolymer CytopTM as the gate dielectric. Using pentacene and N,N -ditridecylperylene-3,4,9,10-tetracarboxylicdiimide PTCDI-C13 , we fabricated complementary inverters of high electrical quality and stability that are almost unaffected by repeated gate bias stress. The comb...

Received April 27, 2012 Revised May 14, 2012 Accepted May 26, 2012 Application of symmetric double gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple process simulation has been developed to reduce the...

This work investigates the intrinsic characteristics of multilayer WSe2 field effect transistors (FETs) by analysing Pulsed I-V (PIV) and DC characteristics measured at various temperatures. In DC measurement, unwanted charge trapping due to the gate bias stress results in I-V curves different from the intrinsic characteristic. However, PIV reduces the effect of gate bias stress so that intrins...