At-speed testing of gigahertz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost high-quality self-test methodologies that can be used by processors to test themselves at-speed. Currently, built-in self-test (BIST) is the primary self-test methodology available. While memory BIST is commonly used for testing embedded...

1 This work has been partially funded by FCT (Portugal), POCTI/ESE41788/2001. Abstract. This paper describes a new tool for Built in Self Test (BIST) design automation and fault emulation (FE). Combinational and/or sequential digital modules may be designed with embedded self-test attributes. Linear Feedback Shift Registers (LFSRs) and Multiple Input Shift Registers (MISRs) are automatically ge...

Test pattern storage is an important problem aaect-ing all Design for Testability (DfT) techniques based on scan-path. Built-In Self Test (BIST) methodologies are used in conjunction to scan-path techniques for reducing the amount of test patterns that must be stored. This paper analyzes two SCAN/BIST approaches and identiies conditions which guarantee that such techniques require shorter test ...

Built-In Self-Test (BIST) provides an effective way to test configurable cores in System-on-Chip (SoC) implementations. We present a case study of the use of dynamic reconfiguration from an embedded processor core to implement BIST for the programmable logic and routing resources in configurable cores in commercially available SoCs. Experimental results from actual implementations include speed...

The development and automatic generation of Built-In Self-Test (BIST) configurations for Atmel AT40K series Field Programmable Gate Arrays (FPGAs) are described. These BIST configurations completely test the programmable logic and routing resources in the core of the FPGA along with the dedicated Random Access Memories (RAMs) dispersed within the array. The BIST configurations are generated usi...

The paper presents a new approach to transparent BIST for wordoriented RAMs which is based on the transformation of March transparent test algorithms to the symmetric versions. This approach allows to skip the signature prediction phase inherent to conventional transparent memory testing and therefore to significantly reduce test time. The hardware overhead and fault coverage of the new BIST sc...

This paper presents a novel approach for test generation and test scheduling for multi-clock domain SoCs. A concurrent hybrid BIST architecture is proposed for testing cores. Furthermore, a heuristic for selecting cores to be tested concurrently and order of applying test patterns is proposed. Experimental results show that the proposed heuristics give us an optimized method for multi clock dom...

-Built-in self-test (BIST) is a design technique that allows a circuit to test itself. It is a set of structured-test techniques for combinational and sequential logic, memories, multipliers and other embedded logic blocks. BIST consists of a controller, and circuits for input excitation and output validation. A BIST circuit comprises a scan monitor with hold logic and a signature generation el...

Power dissipation is a challenging problem in current VLSI designs. In general the power consumption of device is more in the testing mode than in the normal system operation. Built in self test (BIST) and scan-based BIST are the techniques used for testing and detecting the faulty components in the VLSI circuit. Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for...

This paper presents a two-step Built-in Self-Test (BIST) scheme and its implementation for Operational Amplifier (Opamp). In addition to the catastrophic faults, the proposed technique can particularly detect the capacitance variation in the compensation capacitor by combining the current-based test with the offset-based test to detect the physical defects in the Opamp. The circuit-level simula...