Design-for-testability is a very important issue in software engineering. It becomes crucial in the case of OO designs where control flows are generally not hierarchical, but are diffuse and distributed over the whole architecture. In this paper, we concentrate on detecting, pinpointing and suppressing potential testability weaknesses of a UML class diagram. The attribute significant from desig...

This paper presents a method to carry out the register allocation phase of High Level Synthesis with testability considerations. Testability problems are identified and eliminated during this step turning testability/area tradeoff to account. It allows to decrease the cost related to the application of low-level DFT techniques.

Any technology offering zero power dissipation must be reversible. A reversible circuit can envisaged as a cascade of gates only, such Toffoli gate, which has two components: k control bits and target bit (k-CNOT), ≥ 1. Analysing testability issues in is an important phenomenon. new online design-for-testability (DFT) technique for circuits proposed. The authors’ method yields less overhead ter...

The necessary and sucient conditions for an automaton to be locally threshold testable are found. We introduce the polynomial time algorithm to verify local threshold testability of the automaton of time complexity O(n 5) and an algorithm of order O(n 3) for the local threshold testability problem for syntactic semigroup of the automaton. We modify necessary and sucient conditions for piecewise...

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel c...

When test vectors are applied to a circuit, the fault coverage increases. The rate of increase, however, could be circuit-dependent. In fact, the actual rise of fault coverage depends on the characteristics of vectors, as well as, on the circuit. The paper shows that the average fault coverage can be computed kom circuit testability. A relationship between fault coverage and circuit testability...

Fault diagnosis is very important for development and maintenance of safe and reliable electronic circuits and systems. Many k-fault diagnosis methods were put forward such as branch method, node method, loop method, mesh method, cut set method. But the tolerance effect as well as non-linear problems exist and are difficult to deal with. A fault diagnosis method for analog circuit is proposed i...

Runtime testing is emerging as the solution for the integration and assessment of highly dynamic, high availability software systems where traditional development-time integration testing is too costly, or cannot be performed. However, in many situations, an extra cost will have to be invested in implementing appropriate measures to enable runtime tests to be performed without affecting the run...

This paper presents an implemented system for modifying digital circuit designs to enhance testability. The key contributions of the work are: (1) setting design for testability in the context of test generation, (2) using failures during test generation to focus on testability problems, (3) indexing from these failures to a set of suggested circuit modifications. This approach does not add tes...

This paper investigates the relationship between multi-cycle false paths and the testability of sequential circuits. We show that removal of multi-cycle false paths (either by circuit restructuring or by proper state encoding) improves circuit testability, but not as signiicantly as one would expect. We demonstrate the inability of current structure-based scan register selection techniques to s...