In this paper a study has been presented on High Speed(HS) and 79mW Low Power(LP) 16X16 MAC performance of new XOR-Based circuits using transmission gate logic(TG) implemented on 0.65um CMOS DLP/DLM technology. It is shown that our proposed MAC results in better performance than other published MACs due to no DC leakage currents for low power and bypassing unnecessary switching activities with ...

This paper introduces a power-gating scheme appropriate for near-threshold operating of single-phase adiabatic circuits. A transmission gate with MOS bootstrapping scheme is used as the power-gating switch, which is used to reduce energy overhead. CAL (Clocked Adiabatic Logic) circuits are investigated. The analytical model for power-gating adiabatic circuits is constructed, and the energy over...

We address the problem of estimating the average switching activity of combinational circuits under random input sequences. Switching activity is strongly affected by gate delays, and for this reason we use a variable delay model in estimating switching activity. Unlike most probabilistic methods that estimate switching activity, our method takes into account correlation caused at internal gate...

application of quantum-dot is a promising technology for implementing digital systems at nano-scale.  quantum-dot cellular automata (qca) is a system with low power consumption and a potentially high density and regularity. also, qca supports the new devices with nanotechnology architecture. this technique works based on electron interactions inside quantum-dots leading to emergence of quantum ...

An analysis of clock feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. A region map is developed for the TG switch during the period when both devices are turned off. The region map is further divided into zones. From these reg...

In this paper, a novel class of pulsed latches of high speed under minimum energy consumption is designed and implemented in 65-nm CMOS technology. This conditional push-pull pulsed latch adopts a push-pull output stage, which is driven by two split paths with a conditional pulse generator. It is implemented in two versions, respectively, without (CP 3 L) and with (CSP 3 L) shareable conditiona...

In order to go ahead in fierce competition to be a hub port, many major container companies all over the world are making every effort to improve their productivity through high-tech devices and information technology application. In particular, in case of container terminal gate, state-of-the-art technologies such as RFID (Radio Frequency Identification) and OCR (Optical Character Reader) are ...

We designed and fabricated a 4 4 switch in which all interconnections were implemented using passive transmission lines (PTLs). The switch consisted of four identical 2 2 switches connected using PTLs. The 2 2 switch was designed using gate-to-gate passive interconnections. Using the on-chip testing method, we demonstrated 40-GHz operation of the 4 4 switch. To verify the effectiveness of passi...

We measure the real and imaginary conductivity s(k50,v) of a high-mobility two-dimensional electron gas ~2DEG! system at frequencies below and above the momentum scattering rate. The imaginary part of the 2DEG impedance is observed to be inductive, consistent with the Drude model. Using this kinetic inductance, we construct a transmission line by capacitively coupling the 2DEG to an Al Schottky...

We study molecular transistors where graphene nanoribbons act as three metallic electrodes connected to a ring-shaped 18-annulene molecule. Using the nonequilibrium Green function formalism combined with density functional theory, recently extended to multiterminal devices, we show that these nanostructures exhibit exponentially small transmission when the source and drain electrodes are attach...