Tunnel FETs are interesting devices for their steep sub-threshold slopes. In this paper a p+n+in+ tunnel FET is proposed and optimized for a high Ion/Ioff ratio and suitable output characteristics. The proposed tunnel FET has p+in+ structure with a δ-doped n+ region at the beginning of the channel. The proposed structure is extensively studied and the energy bands, transfer characteristics, and...

In this proposed work, a novel single gate F-shaped channel tunnel field effect transistor (SG-FC-TFET) is and investigated. The impact of thickness the source region lateral tunneling length between oxide edge on analog radio frequency parameters are investigated with appropriate drain through 2D-TCAD tool. slender shape enhanced electric crowding at corners which reflect in terms high ON-curr...

There has been significant progress in graphene research since its isolation. The future of graphene for the electronics industry will depend on our ability to grow it or form it from graphite sources with the desired characteristics that meet the requirements of the specific application. The semiconductor industry is still pursuing devices that meet beyond complementary metal oxide semiconduct...

Cellular neural networks (CNNs) are a powerful analog architecture that can outperform the traditional von Neumann architecture for spatio-temporal information processing applications – e.g., image processing, speech recognition, etc. Much existing work reports energy dissipations for CNNs at the chip level, which includes dissipation of sensors, actuators, accompanying digital components, etc....

Compared with a two-dimensional (2D) homogeneous channel, the introduction of 2D/2D homojunction or heterojunction is promising method to improve performance tunnel field-effect transistor (TFET), mainly by controlling tunneling barrier. We simulate 10-nm-Lg double-gated GeSe TFETs and van der Waals (vdW) GeSe/GeTe based on ballistic quasi-static ab initio quantum transport simulation. Two devi...

Over the last decades, the continuous down-scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) enabled faster and more complex chips while at the same time the space and power-consumption was kept under control. However, in the future, the further reduction of the power consumption per unit area will be restricted by a fundamental limit of the inverse subthreshold swing of M...

This research paper explains the effect of dimensions Gate-all-around Si nanowire tunneling field transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors characteristics tunnel transistors. The Silvaco TCAD has been used to study electrical TFET. Output (gate voltage-d...

The variation of the temperature-dependent performance an electronic device is one major concerns in predicting actual electrical characteristics as bandgap semiconducting material varies with temperature. Therefore, this article, we investigate impact temperature variations ranging from 300 to 450K on DC, analog/ radio frequency, and linearity dual stack gate oxide-source dielectric pocket-tun...

In this paper, we proposed a 2-D analytical model for electrical characteristics such as surface potential, electric field and drain current of Silicon-on-Insulator Tunnel Field Effect Transistor (SOI TFETs) with a SiO2/High-k stacked gate-oxide structure. By using superposition principle with suitable boundary conditions, the Poisson’s equation has been solved to model the channel r...