In this paper we propose a system based on a Complex Programmable Logic Device (CPLD) as a physical modeling synthesis engine and a hardware description language (VHDL) to implement the physical modeling synthesis algorithms. An evaluation of VHDL and CPLD technologies for this application was performed. As an example we have programmed the Karplus-Strong plucked string algorithm using VHDL on ...

This paper presents a teaching experience in using VHDL and CPLD in the senior digital design course. The course focus on teaching the top-down design methodology through hands-on experiments. The industrial available tools — Maxplus2, made possible through Altera’s University Program, provide our students a smooth transition from academic concepts to industrial practice. VHDL, the industrial s...

The current state of the art in integrated circuit design is based on the use of special hardware design languages such as VHDL. In the context of the development of an intelligent, knowledge-based debugging aid for VHDL programs, we are dealing with analysis and diagnosis of a subset of VHDL (which is similar to conventional concurrent programming languages). We present an adaptation of conven...

Described are VHDL related methods and experiences from the RASSP programs model year effort. The "Virtual Prototype” development methodology is presented highlighting specific VHDL model views and their interact ions with sof tware design. Performance and Instruction Set Archi tec ture model ing areas o f the methodology are elaborated drawing from the experiences of the Demonstration team. Fi...

In the high-level synthesis domain, the integration of user defined RT components in the algorithmic specification plays an important role. The implementation of VHDL models emulating specific functional and timing behavior at the algorithmic level is expensive and time-consuming. Moreover, particular functional and timing behavior can only be implemented at the RT level, e.g. interrupt handlin...

Testability analysis of VHDL sequential models is the main topic of this paper. We investigate the possibility to obtain information about the testability of a sequential VHDL description before its actual synthesis. The analysis is based on an implicit fault model that injects faults into a BDD based description extracted from the VHDL representation. Such an injection is related to the origin...