The DRAM is a typical bottleneck of a digital system. Moreover, the architectures are getting more complex, which makes their evaluation harder. In this paper, we propose a fast and early estimation of the memory system performance with an actual application in mind. A DRAM simulator, Rascas, developed for this purpose is presented. Rascas is used to study the DRAM behavior with several memory ...

We evaluate the performance of a single chip multiprocessor integrated with DRAM. We compare the performance of this architecture with that of a more conventional chip which only has on-chip SRAM. The DRAM-based architecture with four processors performs an average of 52% faster than the SRAM-based architecture on floating point applications with large working sets. This is performance differen...

Design and synthesis of DRAM based memory systems has been a di cult task in high-level system synthesis because of the relatively complex protocols involved. In this paper, we illustrate a method for topdown design of a DRAM memory interface using a transformational approach. Sequential decomposition of the DRAM memory interface entails extraction of a DRAM memory object from a system descript...

Title of dissertation: SCALABLE AND ENERGY EFFICIENT DRAM REFRESH TECHNIQUES Ishwar Singh Bhati Doctor of Philosophy, 2014 Dissertation directed by: Professor Bruce Jacob Department of Electrical and Computer Engineering University of Maryland, College Park A DRAM cell requires periodic refresh operations to preserve data in its leaky capacitor. Previously, the overheads of refresh operations w...

This paper describes the impact of DRAM process on the logic circuit performance of Memory Logic Merged Integrated Circuit and the alternative circuit design technology to o set the performance penalty Extensive circuit and routing simulations have been performed to study the logic circuit performance degradation when the merged chip is implemented on DRAM process Three logic processes m m and ...

In a chip multiprocessor (CMP) system, where multiple on-chip cores share a common memory interface, simultaneous memory requests from different threads can interfere with each other. Unfortunately, conventional memory scheduling techniques only try to optimize for overall data throughput and do not account for this inter-thread interference. Therefore, different threads running concurrently on...

BACKGROUND As an important cellular stress sensor phosphoprotein p53 can trigger cell cycle arrest and apoptosis and regulate autophagy. The p53 activity mainly depends on its transactivating function, however, how p53 can select one or another biological outcome is still a matter of profound studies. Our previous findings indicate that switching cancer cells in high glucose (HG) impairs p53 ap...

Three-dimensional (3D) integration is promising to provide dramatic performance and energy efficiency improvement to 3D logic-DRAM integrated computing system, but also poses significant challenge to the yield. To address this challenge, this paper explores a way to leverage logic-DRAM co-design to reactivate unused spares and thereby enable the cost-efficient technique to repair 3D integration...

In-memory DBMS enable high query performance by keeping data in main memory instead of only using it as a buffer. A crucial enabler for this approach has been the major drop of DRAM prices in the market. However, storing large data sets in main memory DBMS is much more expensive than in disk-based systems because of three reasons. First, the price for DRAM per gigabyte is higher than the price ...

SOI technology has received high attention for the future high density DRAM applications. The two major requirements in any DRAM technology are long retention time and high charging efficiency. This paper discusses the disadvantages of using bulk silicon and Partially Depleted SOI devices in these terms. It is shown that a DRAM cell built with fully depleted SOI MOSFETs can store data for a lon...