A Vertical Cavity Surface Emitting Laser (VCSEL) driver in 65nm CMOS selectively-enables parallel low-power CMOS drivers to shape the output current waveforms and compensate VCSEL nonlinearities. The CMOS waveform-shaping drivers are AC-coupled allowing them to operate from a 1-V supply to save power, while parallel low-frequency paths provide programmable DC biasing from a 3-V supply. The meas...

The effect of transistors in abutted rows on charge sharing is investigated by changing the configuration this work. 3D TCAD numerical simulations indicate that existence can mitigate occurring probability sharing, especially induced ion striking at vicinity n-well contact. also single event double transient (SEDT) pulse width reduced obviously for strike location near A 65 nm test chip was des...

Two lightweight block cipher families, Simon and Speck, have been proposed by researchers from the NSA recently. In this paper, we introduce Simeck, a new family of lightweight block ciphers that combines the good design components from both Simon and Speck, in order to devise even more compact and e cient block ciphers. For Simeck32/64, we can achieve 505 GEs (before the Place and Route phase)...

There is a demand for portable devices like mobiles and laptops etc. and their long battery life. For high integrity CMOS VLSI circuit design in deep submicron regime, feature size is reduced according to the improved technology. Reduced feature size devices need low power for their operation. Reduced power supply, reduces the threshold voltage of the device. Low threshold devices have improved...

In this letter, a 41-GHz Doherty power amplifier (PA) in standard 65nm CMOS technology is introduced for 5G New Radio (NR) applications. The proposed PA implements the transformer-based parallel-combined structure to enhance power-added efficiency (PAE). A tunable 90-deg hybrid coupler output phase compensation. This work achieves saturated (Psat) of 19.4dBm and an OP1dB 18.6dBm at 41.5GHz unde...

The main objective of the thesis is to implement different architectures of 16-bit adders such as; Ripple Carry Adder (RCA), Manchester Carry Chain Adder (MCCA) and Kogge Stone Adder (KSA), in 65nm CMOS technology and to study their performance in terms of power, operating frequency and speed at near threshold operating regions. The performance of these adders are evaluated and compared with ea...

Previous efforts to reduce SRAM power have included voltage scaling to the edge of sub-threshold [2] or into the sub-threshold region [3], but only for idle cells. Although some published SRAMs operate at the edge of sub-threshold, none function at sub-threshold supply voltages compatible with logic operating at the minimum energy point. The 0.18μm memory in [4] provides one exception. Consisti...

The urge of high performance and dynamic functionalities in an integrated circuit has led to aggressive technology scaling over the years. The supply voltage (VDD), device threshold voltage (Vth) and the device geometry are expected to be scaled further with this trend. Which results in reducing the short channel effects and increased transistor OFFstate current (IOFF). Additionally leakage cur...

This paper provides a comparative study of the proposed global clock distribution methods for high-speed digital integrated circuits. Both non-networked and distributed schemes such as travelling and standing wave clock distributions have been reviewed. Performance metrics are described and qualitatively discussed and non-networked approaches were simulated in a low-power 65nm CMOS process.

CMOS has dominated the digital design space almost since its discovery. Alternative design styles such as domino logic, complementary pass gate logic, and others have been proposed and implemented, but none achieved the penetration and reach of the standard CMOS library. These other designs often have benefits for certain applications but none have been able to unseat CMOS as the de facto desig...