This article focuses on how to do meaningful power calculations and sample-size determination for common study designs. There are 3 important guiding principles. First, certain types of retrospective power calculations should be avoided, because they add no new information to an analysis. Second, effect size

To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, sum...

Background and Objectives: Digital signal processors are widely used in energy constrained applications in which battery lifetime is a critical concern. Accordingly, designing ultra-low-energy processors is a major concern. In this work and in the first step, we propose a sub-threshold DSP processor. Methods: As our baseline architecture, we use a modified version of an existing ultra-low-power...

Computing Leakage Current Distributions and Determination of Minimum Leakage Vectors for Combinational Design. (May 2006) Kanupriya Gulati, B.E., University of Delhi Chair of Advisory Committee: Dr. Sunil Khatri Analyzing circuit leakage and minimizing leakage during the standby mode of operation of a circuit are important problems faced during contemporary circuit design. Analysis of the leaka...

Reconfigurable optical add/drop multiplexers (ROADMs) can be classified into three categories based on their underlying switching technologies. Category I consists of a single large optical switch; category II is composed of a number of small optical switches aligned in parallel; and category III has a single optical switch and only one wavelength being added/dropped. In this paper, to evaluate...

Power dissipation is a challenging problem in current VLSI designs. In general the power consumption of device is more in the testing mode than in the normal system operation. Built in self test (BIST) and scan-based BIST are the techniques used for testing and detecting the faulty components in the VLSI circuit. Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for...

-An increasing constraint in implementing algorithms in digital signal processors is low power design. In order to avoid time consuming and uneconomic redesigning it is essential to optimise the sources of power consumption in the earliest possible stage in the IC design cycle. This paper presents CapCount, a novel high-level dynamic power estimation tool, operating as an add-on tool to Synopsy...

Although performed by members of all three domains of life, the archaeal version of N-glycosylation remains the least understood. Studies on Haloferax volcanii have, however, begun to correct this situation. A combination of bioinformatics, molecular biology, biochemical and mass spectrometry approaches have served to delineate the Agl pathway responsible for N-glycosylation of the S-layer glyc...