This paper deals with Enhanced Phase Locked Loop Control scheme for Distributed Static Compensator (DSTATCOM) in the distribution system. The proposed control scheme based DSTATCOM eliminates current harmonics, maintains unity power factor at source, zero voltage regulation and load balancing. The Enhanced Phase Locked Loop (EPLL) Control scheme is based on Digital Signal Processing (DSP) which...

Phase locked loop (PLL) is a technique which has contributed significantly toward the technology advancement in communication and motor servo control systems. Inventions in PLL schemes combining with novel integrated circuit have made PLL devices important system components. The development of better modular PLL integrated circuit is continuing. As a result, it is expected that it will contribu...

In this paper, we describe a pulse stream neural network approach for realising combinational and sequential logical functions, to be henceforth referred to as Digital Pulse Logic. The elemental unit or neuron is based on a modified Phase Locked Loop, using which we design digital gates and sequential blocks. Such implementations offer very wide noise margins and are thus more robust in compari...

Synchronization algorithms are of great importance in control of grid-connected inverters as an integral part of distributed power generation units such as photovoltaic systems. A new all-digital closed-loop phase-locked algorithm for the synchronization signals of three-phase grid-connected inverters is presented even considering seriously distorted and variable-frequency utility conditions. T...

In a previous work we proposed a phase-lock structure called the time-delay digital tanlock loop (TDTL). This digital phase-locked loop (DPLL) performs nonuniform sampling and utilizes a constant time-delay unit instead of the constant 90-degrees phase-shifter used in conventional tanlock structures. The TDTL reduces the complexity of implementation and avoids many of the practical problems ass...

The All-Digital Phase-Locked Loop has several advantages when compared with traditional charge-pump based PLL. We will introduce some of its advantages in this paper, showing how they can be used to improve the system’s performance. In addition, performance limitations of the system will be discussed.

This paper presents a time amplifier design that improves time resolution using an inverter chain delay in SR latches. Compared with the conventional design, the proposed time amplifier has better characteristics such as higher gain, wide range, and small die size. It is implemented using 0.13 μm standard CMOS technology and the experimental results agree well with the theory. key words: time a...

A Digital PLL is designed with improved acquisition time and power efficiency. The implemented D-PLL can operate from 6.54MHz to 105MHz with a power dissipation of is 7.763μW (at 210MHz) with 1.2V supply voltage. The D-PLL is synthesized using cadence RTL compiler in 45nm CMOS process technology.

A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6m CMOS process. Test...

This paper presents recent work on reconfigurable all-digital radio architectures. We leverage the flexibility and scalability of synthesized digital cells to construct reconfigurable radio architectures that consume significantly less power than a software defined radio implementing similar architectures. We present two prototypes of such architectures that can receive and demodulate FM and FR...