Technology dependent logic optimization is usually carried through a sequence of design rewiring operations. In [18] a new design rewiring method is proposed that combines error diagnosis and correction techniques with ATPG. In this work, we examine its complexity and we arrive to a new set of results with interesting theoretical and practical applications. We also present experiments that conf...

The digital logic rewiring technique has been shown to be one of the most powerful logic transformation methods . It has been proven that rewiring is able to further improve some already excellent results on many EDA problems, ranging from logic minimization, partitioning, FPGA technology mappings to final routings. Previous studies have shown that ATPG-based rewiring is one of the most powerfu...

Abstract Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve quality, compared with conventional automatic pattern generation (ATPG) approaches, which target only at the boundaries of cells. The CAT methodology consists two stages. Stage 1, based on dedicated analog simulation, characterization per cell identifies cell-level detects cell-internal de...

Function Approximation (FA) representations of the state-action value function Q have been proposed in order to reduce variance in performance gradients estimates, and thereby improve performance of Policy Gradient (PG) reinforcement learning in large continuous domains (e.g., the PIFA algorithm of Sutton et al. (in press)). We show empirically that although PIFA converges significantly faster ...

Logic optimization is the step of the VLSI design cycle where the designer performs modifications on the design obtained to satisfy different constraints such as area, power or delay. In this paper we propose a novel ATPGbased optimizationmethodology that borrows from previous design error diagnosis and correction techniques. We also present examples and experiments that indicate that our appro...

Due to the rising performance and decreasing feature sizes of today’s designs, the likelihood of delay defects increases. Therefore, transition fault testing is widely used to ensure that the delivered chips are free of fabrication defects. Due to the use of scan testing, the switching activity in the Circuit Under Test (CUT) is typically several times higher than during normal functional opera...

our verification program is especially customized to focus on how to trim down the search space, it does not use the guidance popularly adopted in a sequential ATPG program to find a test quickly if the two circuits are not equivalent. Hence, our program should be integrated with an original sequential ATPG program as a dual-program to handle different situations. For example, our verification ...