We present a new approach to automatic test pattern generation for very large scale integrated sequential circuit testing. This approach is more eecient than past test generation methods, since it exploits knowledge of potential circuit defects. Our method motivates a new combinatorial optimization problem, the Tour Covering Problem. We develop heuristics to solve this optimization problem, the...

We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have been broken by using scan flip-flops (FF’s) and the control and data path parts are individually 100%testable, the composite circuit may not be easily testable by gatelevel sequential automatic test pattern generation (A...

Due to ever increasing design sizes, more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently, SAT-based approaches for test pattern generation have been shown to be very efficient even on large industrial circuits. But these SAT-based techniques are not always superior to classical ATPG approaches. An integration of SAT-based engines into the classical ATPG flow c...

In this paper, we propose a technique that utilizes the genetic algorithm for various VLSI circuits. In GA, we proposed the method of automatic test pattern generation (ATPG) is used to generate test vectors. Experiment results showed that the proposed algorithm reduce the complexity of the circuits and also the execution time. The design is realized using VHDL and then fabricated on FPGA.

Test case generation is essential to software test. Software test efficiency can be greatly improved through test case automatic generation. AADL Behavior Annex is an extension of AADL which can describe detailed behavior of AADL component. In this paper, we discuss a test case automatic generation method based on the AADL Behavior Annex. This method contains two parts: automatic generation of ...

Timing-related defects are a major cause for test escapes and field returns for very-deep-sub-micron (VDSM) integrated circuits (ICs). Small-delay variations induced by crosstalk, process variations, power-supply noise, and resistive opens and shorts can cause timing failures in a design, thereby leading to quality and reliability concerns. We present the industrial application and case study o...

This paper shows an automated flow to generate test vectors for digital IC-designs in an academic environment. The tool “Tetramax” from Synopsys has been used for Automatic Test Pattern Generation. The ATS200 hardware verification tester together with IMS software provides a structured environment for prototype analysis and for real-time comparison of the design performance against the simulate...