An offset voltage adjustment technique, which can be used to reduce the offset voltage of the buffer amplifier in the liquid-crystal display signal driver, is proposed. This adjustment, which is finished before driving the display panel, does not need to be adjusted for every row scanning cycle and does not increase the settling time. An experimental prototype output buffer implemented in a 0.3...

In CMOS multistage clock buffer design, the duty-cycle of clock is liable to be changed when the clock passes through several buffer stages. The pulse-width may be changed due to unbalance of the pand n-OS transistors in the long buffer. This paper describes a delay locked loop with double edge synchronization for use in a clock alignment process. Results of its SPICE simulation, that relate to...

This paper presents a 60 GHz CMOS I/Q receiver for the high-speed wireless communication system. It consists of low noise amplifier, single-to-differential (S2D) passive mixer, buffer amplifier with generator, and wideband baseband (BBA) stage. The measured conversion gain 51 dB is achieved. bandwidth 300 MHz achieved from 57 to GHz. 90° tandem coupler was implemented signal generation, which h...

This paper very shortly describes some hardware solutions of central processor (CPU) of BESM-6. CPU had very deep instruction pipe with an associative buffer for instructions and an associative buffer for data with original protocol. Logical and storage elements used only domestic discrete components. Main logical unit based on differential amplifier with pyramid of rich diode logic and parapha...

a novel low noise trans-impedance amplifier is proposed using low cost 0.18 µm cmos technology. a resistive-capacitive feedback is used to extend the bandwidth of the amplifier. as the structure is inductor less, it is suitable for low cost integrated optical interconnects. in this paper improved particle swarm optimization have applied to determine optimal trans-resistance and noise of propose...

a digital look-up table adaptive predistortion technique using a six-port receiver for power amplifier linearization is presented. the system is designed in ka-band for a dvb-s2 satellite link. we use a six-port receiver at the linearizationloop in place of classic heterodyne receivers. the six-port receiver is implemented by the use of passive microwavecircuits and detector diodes. this approa...

The performance analysis of the two-stage CMOS operational amplifiers employing Miller capacitor in conjunction with the common-gate current buffer is presented. Unlike the previously reported design strategy of the opamp of this type, which results in the opamp with a lower power supply requirements, better phase margin and better speed. The Opamp is designed to exhibit a unity gain frequency ...

This work proposes a RX front-end structure, which is used for channel equalization of 25Gb/s high-speed links. design includes two parts, linear equalizer and decision feedback equalizer. Linear consists the variable gain amplifier, continuous-time output buffer, provide 19dB peaking around Nyquist frequency. The half-rate with one speculative tap cascaded after buffer to eliminate residual in...