The present paper Performance improvement in high speed low power out put Buffer amplifier for large –LCD applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with limited power consumption by exploiting a slew detector which monitors the output voltage of the inp...

This paper presents an overview of recent advances on modeling and layout optimization of devices and interconnects for high-performance VLSI circuit design under the deep submicron technology. First, we review a number of interconnect and driver/gate delay models, which are most useful to guide the layout optimization. Then, we summarize the available performance optimization techniques for VL...

This paper gives a detailed dkcussion of the short-circuit compouentin the totaf powerdissipationin CMOS circuits, on the basisof an elementaryCMOS inverter. Designconsiderationsare givenfor CMOS buffer circuits, based upon the results of the dissipation discussion,to increasecircuit performance.

A 5Gb/s optical receiver front-end for optical interconnection is presented in this paper. A transimpedance amplifier (TIA), limiting amplifiers (LA), output buffer and a bias circuit are integrated in deep Nwell 0.18 m CMOS technology. As the input current amplitude is 30 A, the differential output voltage is achieved to be 124 mV. The linear gain is 78.8dB and consumes 200mW under 1.8V supply...

A novel reconfigurable hybrid single electron transistor/MOSFET (SETMOS) circuit architecture, namely, reconfigurable pseudo-NMOS-like logic is proposed. Based on the hybrid SETMOS inverter/buffer circuit cell, reconfigurable pseudo-NMOS-like logics that can work normally at room temperature are constructed. This kind of reconfigurable logic can implement up to 2n sorts of functions at n inputs...

This paper describes a two-stage method to generate test sets for I testing and to determine the leakage DDQ fault coverage for given test pattern sets. The method has been integrated within a fault simulator. Furthermore, it will be proved that any complete test pattern set generated for stuck-at faults detects all leakage faults caused by intra-gate shorts within a static CMOS circuit if the ...

Introduction: The class-AB buffer amplifier is widely used for driving heavy resistive or capacitive loads [1–4]. Some buffer amplifiers employ a pseudo-source follower, which has a pair of complementary common-source transistors with two feedback loops consisting of a pair of complementary error amplifiers [1–2]. Employing error amplifiers introduces the excess phase shift and makes the freque...

This report describes our work detailing the operation and performance of TCP-based transport protocols (Reno, BIC, and CTCP) on “Layer-1” circuits, in which a Gigabit Ethernet port on an end host has been directly mapped to a SONET circuit of lower rate (e.g., a 155 Mbps OC3). The switch uses IEEE 802.3x flow control to prevent the sender from overwhelming the switch’s buffer. Current equipmen...

In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18μm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circui...

In this paper we investigate single electron tunneling (SET) devices from the logic design perspective, using the SET tunnel junction’s ability to control the transport of individual electrons. More in particular, we present the implementation of a Full Adder using SET threshold gates. First, we augment the threshold gates with an active buffer in order to overcome feedback effects which can ap...