In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency....

This paper presents a new method for designing a reversible carry look-ahead adder (RCLA) based on dynamic programming. In this method, we propose a faster technique for generating carry output, which also outperforms the existing ones in terms of number of operations. In addition, we design a compact reversible carry look-ahead circuit based on the proposed technique. In order to optimize our ...

Precision measurements in the neutrino sector are becoming increasingly feasible due to the development of relatively high-rate experimental capabilities. These important developments command renewed attention to the systematic corrections needed to interpret the data. Hadronic multi-particle final state measurements made using CLAS at Jefferson Lab, together with a broad theoretical effort tha...

A digit-recurrence algorithm for computing the Euclidean norm of a 3-dimensional vector is proposed. Starting from the vector component with the highest order of magnitude as the initial value of partial result, correcting-digits produced by the recurrence are added to it step by step. Partial products of the squares of the other two components are added to the residual, step by step. The addit...

The main result of this paper is the development of a low depth carry lookahead addition technique based on threshold logic. The adders designed using this method are shown to have a very low logic depth and therefore reduced area and improved speed over conventional logic implementations.