Clock routing is critical in nano-scale VLSI circuit design. Clock routing needs to be precise to minimize circuit delay. Clock signals are strongly affected by technology scaling, the long global interconnect lines become highly resistive as line dimensions are decreased. The control of clock skew can also severely limit the maximum performance of the entire system and create catastrophic race...

This paper gives the Growth of the semiconductor industry has made the design of integrated circuits in daunting task. The ASIC design flow is differs the design of the clock network until late in the design of cycle when the cell placement is done and the location of the registers are known. And the clock tree estimation always based on best guess of the ASIC planner. In additional the critica...

True single phase clock logic techniques, e.g. with alternating arranged Nand P-logic cells, yield easy to design circuits with standard cells and high speed potential. The disadvantages are a difficult clock tree design and high power consumption. To realize every logic function, dual rail or differential styles are chosen which increase clock load. This paper presents a method to speed up dyn...

The paper describes a system that can automatically generate tree adjoining grammars from abstract specifications. Our system is based on the use of tree descriptions to specify a grammar by separately defining pieces of tree structure that encode independent syntactic principles. Various individual specifications are then combined to form the elementary trees of the grammar. The system enables...

Phylogenetic trees inferred using commonly-used models of sequence evolution are unrooted, but the root position matters both for interpretation and downstream applications. This issue has been long recognized; however, whether the potential for discordance between the species tree and gene trees impacts methods of rooting a phylogenetic tree has not been extensively studied. In this paper, we ...

This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed GatedClock Tree Synthesizer ...

decision trees as one of the data mining techniques, is used in credit scoring of bank customers. the main problem is the construction of decision trees in that they can classify customers optimally. this paper proposes an appropriate model based on genetic algorithm for credit scoring of banks customers in order to offer credit facilities to each class. genetic algorithm can help in credit sco...

This paper presents circuit design of a low-power delay buffer. The proposed delay buffers are accessed sequentially, and it operates as a ring-counter addressing strategy. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Double-edge-triggered (DET) flip-flops and the C-element gated-clock strategy is implemented in the delay b...