This paper argues in favor of adaptive reconJiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconJigurable structure to recover ...

A Radial Basis Function Network (RBFN) classifier for hard fault location in CMOS analogue circuit is presented. The network is trained by means of a fault dictionary containing the faulty circuit response, which is obtained by simulating the supply current dynamic response.

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circ...

The P1149.4 mixed-signal boundary scan standard is demonstrated with a CMOS integrated circuit. Design issues and characterization data are presented.

Application specific full custom design integrated circuit is a methodology for making a logic cell, circuit or layout specification. Full custom design circuit is the part of Application specific integrated circuit. A gate array or uncommitted logic array as an approach to the design and manufacture of application specific integrated circuit. It requires custom chip fabrication using a complet...

This paper presents the latest implementation of the SIMD Current-mode Analogue Matrix Processor architecture. The SCAMP-3 vision chip has been fabricated in a 0.35μm CMOS technology and comprises a 128×128 general-purpose programmable processor-perpixel array. The architecture of the chip is overviewed and implementation issues are considered. The circuit design of the analogue register is pre...

A CMOS analogue circuit for Gaussian noise generution as well as a novel circuitfor transforming Gaussian noise into uniform noise, hoth.designed/or operating with a supply voltoge o/ I . S K arepresented. Both circuits are optimizedfor U 0 . 3 5 ~ standord CMOS technology using an equation-based design methodology based on generic algorithms. Electrical simulations demonstrate that high noise ...

We numerically investigate the possibility of using Tunnel field-effect transistor (TFET) in a 32 kHz crystal oscillator circuit to reduce power consumption. A simulation using SPICE (Simulation Program with Integrated Circuit Emphasis) is carried out based on a conventional CMOS transistor model. It is shown that the power consumption of TFET is one-tenth that of conventional low-power CMOS.

An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of inter...

In Analog circuit design field, current reference circuit is mostly used for constant current supply to the circuits, so that their function runs properly. This work gives a circuit that operates with minimum operating voltage and current, CMOS current generator circuit and presents its performance with circuit simulation in 180nm UMC CMOS technology. The designed circuit has four sub parts sta...