CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers. (August 2009) Rui Xu, B.S. , Southeast University, China; M.S., Southeast University, China Chair of Advisory Committee: Dr. Cam Nguyen Ultra-wideband technology (UWB) has received tremendous attention since the FCC license release in 2002, which expedited the research and development of UWB technologies on consumer p...

The readout of detector arrays requires the monolithic or hybrid integration of a integrate circuit multiplexer with the detector array. In most LWIR and VLWIR applications, a hybrid approach is used. For example, the detector array may be built from HgCdTe and the readout integrated circuit may be silicon CMOS [1]. The two integrated circuits are mated through a bump-bonding process in which e...

implementations utilize a CMOS inverter to obtain a sigmoid response, making the output wave form process sensitive, i.e. making it unpredictable from one integrated circuit to another [5]. predictable output independent of process parameters and thermal effects . Other strengths in this design are its speed and the fact that each weight is fully programmable with up to eight bits of resolution...

SiSMA (Simulator for Statistical Mismatch Analysis) is a CAD tool for the statistical analysis of analog CMOS integrated circuits affected by technological tolerance effects including device mismatch.

A 0.13μm CMOS clock-harvesting receiver is presented which extracts a 21Hz clock embedded within the GSM standard for the wake-up of a wireless sensor network. In active mode, the receiver achieves -87dBm sensitivity with 57μs of jitter at the output while consuming 126μW. The receiver is optimized for heavy duty-cycling with a sleepmode power consumption of only 81pW. Index Terms — Analog inte...

This paper introduces a low cost near-field mapping system. This system scans automatically and dynamically, in the time domain, the magnetic field emitted by integrated circuits during the execution of a repetitive set of instructions. Application of this measurement system is given to an industrial chip designed with a 180nm CMOS process. This application demonstrates the efficiency of the sy...

Surface temperature measurements were performed with a Scanning Thermal Microscope. We aim at proving an eventual sub-micrometric resolution of this metrology when using a wollaston wire probe of micrometric size. A dedicated CMOS device was designed with arrays of lines 0.35μm in size with 0.8 μm and 10μm periods. Integrated Circuits with or without a passivition layer were tested. To enhance ...

The second generation current conveyor CCII is introduced in this paper as a most versatile analog building block for realization of many other active circuits and applications. Short overview of interesting connections, using modular approach of design, with CCII are presented here, as well as two topologies of the conveyor, realized in CMOS technology, including their measured parameters.

This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for GSM/GPRS/EDGE, in order to reduce power and die area as desired for cellular applications. A 2.5G multimode architecture is implemented in 0.13μm CMOS technology occupying 1.0mm and dissipating only 1.3mW in fastest EDGE data transmission mode.