Recent advances of superconducting single-flux-quantum (SFQ) circuit technology make it attractive to investigate computing systems using SFQ circuits, where arithmetic circuits play important roles. In order to develop excellent SFQ arithmetic circuits, we have to design or select their underlying algorithms, called hardware algorithms, from different point of view than CMOS circuits, because ...

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CM...

An on-chip voltage supply regulator for subthreshold-operated CMOS logic LSIs is proposed. The regulator transforms lithium battery voltage 3 V to low supply voltage 0.4-0.5 V for subthreshold-operated CMOS logic LSIs. It monitors the gate delay in the LSI and produces an appropriate supply voltage such that the delay is equal to a value determined by a built-in capacitor-resistor reference. We...

Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to transistor leakage of low-order and high-order basic logic gates. The NAND and NOR gates have been designed using different design styles and circuit topologies, including complementary CMOS, partitioned logic and complem...

This paper introduces two new cells for Logic-inMemory (LiM) operation. The first novelty of these cells is the resistive RAM configuration that utilizes a Programmable Metallization Cell (PMC) as non-volatile element. CMOS transistors and ambipolar transistors are used as processing and control elements for the logic operations of the LiM cells. The first cell employs ambipolar transistors and...

In this paper circuit implementations of cellular processor arrays intended for image processing applications are discussed. It is demonstrated that a departure form the standard CNN model can lead to a significant improvement when processing binary (black/white) images. An asynchronous cellular logic array circuit is presented, which is capable of simulating trigger-waves in an excitable mediu...

Dynamic logic families offer good performance over traditional CMOS logic. This is due to the comparatively high noise margins coupled with the ease of implementation. The main drawbacks of dynamic logic circuits are lack of design automation, charge sharing, feedthrough, charge leakage, singleevent upsets, etc. But these draw backs can be eliminated using domino and NORA circuits but still lac...

this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit f...

1.1. Digital IC Technologies and Logic-Circuit Families The chart in Figure 1 shows the major IC technologies and logic-circuit families that are currently in use. Members of each family are made with the same technology, have a similar circuit structure, and exhibit the same basic features. Each logiccircuit family offers a unique set of advantages and disadvantages. In the conventional style ...

Adiabatic logic is used to minimize the energy loss during operation of the circuit. Using two-phase adiabatic static CMOS logic (2PASCL) the power consumption can be reduced. This paper compares the power consumption of Static Energy Recovery Full Adder(SERF) and the proposed full adder using two phase adiabatic static CMOS logic(2PASCL). The average power consumption of proposed full adder is...