Computer–added design of single-electron nanoelectronic circuits on quantum majority components has been implemented. Proposed methods building logic-arithmetic computing devices the combinational type, which implement an almost complete system logical functions in both and Boolean bases. Quantum cellular automata is a technology that emerged two decades ago, values states correspond to positio...

In this paper a solution is given for the problem to determine the duration of a parallel asynchronous multi–step process in a homogeneous system of combinational logic. In such a system the problem arises if the processors have different speeds and input data. If so each processor “knows” its own data and the type of the process but in general has no information about the speed of the other pr...

The problem of checking whether a system of incompletely specified Boolean functions is implemented by the given combinational circuit is considered. The task is reduced to testing out if two given logical descriptions are equivalent on the domain of one of them having functional indeterminacy. We present a novel SAT-based verification method that is used for testing whether the given circuit s...

Three modular multiplication algorithms are described and compared: the so-called Multiply and Reduce, the Shift and Add, and finally, the Montgomery product. An estimation of the cost of their combinational implementation using Xilinx FPGAs family is calculated. Practical results in term of area, delay, and power for both combinational and completely sequential implementations are presented.

Multivalve logic is a reliable method for defining, analyzing, testing and implementing the basic combinational circuitry with VHDL simulator. It offers better utilization of transmission channels because of its high speed for higher information carried out and it gives more efficient performance. One of the main realizing of the MVL (ternary logic) is that reduces the number of required comput...

In this paper, we consider the problems of identiication of delay-fault-sensitive components in a pipelined combinational circuit, and of circuit modiication to improve the circuit's tolerance of delay faults. The results assume purely combinational logic, and xed gate delays calculated under oating delay mode.

author = "Sin Man Cheang and Kin Hong Lee and Kwong Sak Leung", title = "Designing Optimal Combinational Digital Circuits Using a Multiple Logic Unit Processor", booktitle = "Genetic Programming 7th European Conference, EuroGP 2004, Proceedings", year = "2004", editor = "Maarten Keijzer and Una-May O'Reilly and Simon M. Lucas and Ernesto Costa and Terence Soule", volume = "3003", series = "LNCS...

In the paper an application of evolutionary algorithm to design and optimization of combinational digital circuits with respect to transistor count is presented. Multiple layer chromosomes increasing the algorithm efficiency are introduced. Four combinational circuits with truth tables chosen from literature are designed using proposed method. Obtained results are in many cases better than thos...

Reliability analysis of combinational circuits has become imperative these days due to the extensive usage of nanotechnologies in their fabrication. Traditionally, reliability analysis of combinational circuits is done using simulation or paper-and-pencil proof methods. But, these techniques do not ensure accurate results and thus may lead to disastrous consequences when dealing with safety-cri...