In this paper, we proposed a test data compression scheme targeted for minimizing the amount of test data. The proposed scheme can reduce the test application time and minimize the amount of compressed test data, which reduces the size of data memory in ATE and the time needed to transfer test data. A decoder design is also presented. Experimental results on ISCAS benchmark circuits show that t...

This paper presents a low power strategy for test data compression and a new decompression scheme for test vectors. In our method, we propose an efficient algorithm for scan chain reordering to deal with the power dissipation problem. Further, we also propose a test slice difference (TSD) technique to improve test data compression. It is an efficient method and only needs one extra scan cell. I...

and contributions The high test data volume and long test application time are two major concerns for testing scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction. This dissertation thesis presents a new t...

This paper presents a pattern run-length compression method. Compression is conducted by encoding 2 runs of compatible or inversely compatible patterns into codewords in both views either inside a single segment or across multiple segments. With the provision of high compression flexibility, this method can achieve significant compression. Experimental results for the large ISCAS’89 benchmark c...

paulownia is one of the fast-growing species that was attended to supply industrial requirement in recent years. the application of this species is limited because of low density, so wood modification via compression and densification is an effective method. for this purpose, the paulownia boles were prepared from shastkalateh forest and cut into blocks with 60×20×20 mm dimension. the variable ...

In this paper, complementary Huffman coding techniques are proposed for test data compression/decompression of complex SOC designs during manufacturing testing. Instead of the compatible relationship between test data blocks, complementary features between test blocks are also exploited. Based on this property, more test data blocks can share the same codeword and the size of the modified Huffm...

This paper proposes a new test data compression method for low power testing. To improve compression ratio, the proposed scheme uses the modified input reduction and novel techniques, a new scan flip-flop reordering algorithm and a newly proposed one block compression. The proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous wo...