In this paper the design of a low power sigma-delta modulator with dynamic biasing is presented. This design uses simple analog and digital components to achieve the low power purpose. In order to get a 12-bit resolution over the 4-kHz signal bandwidth for voice band applications such as PCM CODECs, an optimum choice is the second order modulator with an oversampling ratio of 128 and sampling f...

A 0.6-V 34-μW delta–sigma modulator implemented by using a standard 0.13-μm complementary metal–oxide– semiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different ...

In this paper, a reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The modulator consists of two sub-blocks and has a single bit output which makes it best for this application. A good shaping of quantization noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this mod...

Aim of This work is to Design a second order discrete time sigma delta modulator for low frequency high resolution applications, which can be used in data converters (sigma delta ADC) where high resolution is required for more accuracy in signal processing’s. A real world is analogue but easier to process digital data ex: speech, image processing’s. Analog signal contains too much unnecessary d...

Design techniques for sigma-delta modulators from communications are applied and adapted to improve the spectral characteristics of high frequency power electronic applications. A high frequency power electronic circuit can be regarded as a quantizer in an interpolative Σ∆ modulator. We review one dimensional sigma-delta modulators and then generalize to the hexagonal sigma-delta modulators tha...

approved: Gabor C. Temes This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC c...

In a digital class D power amplifier, the distortion is introduced into the input signal being amplified in power stage, due to the effect of power supply noise. A method used to eliminate the distortion is presented in the paper. This method is adding correction factors to all integrators of Delta-Sigma modulator, and introducing power supply noise to the input of the class D power amplifier a...

Sigma-delta modulator based digital-to-analog converters (DAC) have offered low-frequency designers a highly linear, high resolution data converter architecture that is highly amenable to integration with complex digital systems. Increasingly these data converters have been used to deliver all the power needed. In wireless applications, it is increasingly desirable to apply low-frequency sigma-...

This paper presents review on system level design of continuous time sigma delta modulator. A continuous time approach offers high accuracy with respect to discrete time modulator. Unity gain frequency and power can be achieved by continuous time design. as the sigma delta modulators are mainly implemented as discrete time circuits , a continuous time approach provides significant advantages fo...