In this paper, we propose a novel multiplexer-based full adder design, denoted as MUXFA, by using regular modules for arithmetic applications. The MUXFA full adder is composed of three identical modules, in which each module separately operates for XOR-XNOR function, sum function, and carry function. The structure of the multiplexer-based full adder can be easily constructed by merely a single ...

In this review paper different design techniques of multi bit adder are deliberate using linear parameters logic gates. The comparison is carried by several parameter mainly focus on a number of linear threshold gates, a number of CMOS transistor, power dissipation, power delay product (PDP), average power dissipation time delay and size of the full adder circuit. Adder circuits basically imple...

A standard cell based gate level synchronous full adder design is presented in this paper. The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP), even in comparison with the full adder element that has been made available as part of two commercial standard cell libraries viz. the high-speed 130nm Faraday (UMC) b...

RC4 Stream cipher is well known for its simplicity and ease to develop in software. But here, in the proposed design we have heighlighted the modified hardware implémentation of RC4. As RC4 is the most popular stream cipher. The proposed design performs reading and swapping simultaneously in one clock cycle. The proposed design also highlights the adder part which enhances the architecture spee...

In this paper, we assimilate and integrate two recent developments in prefix adder design and theory to create a fault-tolerant, real-time reconfigurable prefix adder. By exploiting the inherent redundancy of a Kogge-Stone adder we are able to extract signals to detect and correct from a single-fault. Our 16-bit design consumes less than 44% the hardware overhead of a comparable triple modular ...

Addition is a fundamental arithmetic operation which is used in different applications such as digital signal processing (DSP) and microprocessors. Single bit adder is the main component of any arithmetic circuit. This paper presents the design of new split-path Data Driven Dynamic (sp-D3L) full adder circuit. Power consumption of proposed adder varies from 0.584 nW to 2.914 nW with variation i...

In this paper the design of a new high-speed current mode BiCMOS logic circuits isproposed. By altering the threshold detector circuit of the conventional current mode logic circuitsand applying the multiple value logic (MVL) approach the number of transistors in basic logicoperators are significantly reduced and hence a reduction of chip area and power dissipation as wellas an increase in spee...

The goal of this paper is to present architectures that provide the flexibility within a regular adder to augment/decrement the sum of two numbers by a constant. This flexibility adds to the functionality of a regular adder, achieving a comparable performance to conventional designs, thereby eliminating the need of having a dedicated adder unit to perform similar tasks. This paper presents an a...

A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In t...

In this paper, a proposed 1-bit hybrid full adder design employing both transmission gate logic and complementary metal– oxide–semiconductor (CMOS) logic is reported. The design is implemented for 1-bit Ripple Carry Adder and then is extended for 64-bit Ripple Carry Adder. The circuit is implemented using Mentor Graphics tools 130nm technology. The performance parameters such as delay, area, to...