The integrity and issues related performance associated with scaling Si MOSFET channel length promotes research in new device SOI, double gate and GAA MOSFET. In this paper, we pr novel characteristic of horizontal rectangular gate MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some para...

This work presents an Improved Charge Sheet compact Model (ICSM) especially valuable for distortion analysis, where precise calculation of derivatives of at least third order is required. A new expression for the charge is used in the calculation of the current. Vertical electric field, mobility and DIBL are represented using previously reported for other purposes more precise expressions. The ...

This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I on/I off current ratio is over 10(8) A/A for L g = 1 μm. Using a th...

To extend the use of CMOS technology beyond 14 nm node technology, new device materials are required that can enhance the performance of MOSFETs. The use of high-k materials in double gate (DG) MOSFET can triumph over the problem of power dissipation and leakage current. In this paper, we investigated various high-k dielectrics as the gate oxides in a 12 nm SOI FinFET and the performance potent...

This paper investigates the effect of gate electrode work function in 30 nm gate length conventional and junctionless FinFETs using technology computer-aided design (TCAD) simulations. DC parameters, threshold voltage (vt), drive current (Ion) and output resistance (Ro), and RF parameters, unity gain cutoff frequency (ft), non-quasi static (NQS) delay and input impedance (Z11) are investigated....

Device miniaturization is an important part of VLSI design, which refers to reduction in dimension of device by keeping all other characteristic constant. As technology node is moving in submicron region, the performance of the device degrades due to short channel effects and narrow channel effects. The key issues due to these effects are draininduced-barrier– lowering (DIBL), leakage current, ...

In this paper we look at the quantitative picture of fringing field efSects by use of high-k dielectrics on the 70 nm node CMOS technologies. By using Monte-Carlo based techniques, we extract the degradation in gate-to-channel capacitance and the internal, external fringing capacitance components for varying values of K. Our results clearly show the decrease in external fringing capacitance, in...