The rapid increase in digital signal processing (DSP) applications has generated a strong demand for electrical engineers with DSP backgrounds; however, the gap between industry needs and university curricula still exists. To answer this challenge, a sequence of innovative DSP courses that emphasize hands-on experiments and practical applications were developed for continuing education in elect...

Most of the existing Digital Signal Processors (DSPs) are optimized for a fast and e cient computation of the Fast Fourier Transform (FFT). However, there are only two oating-point DSPs available, which perform the butter y operation of a FFT in 4 processor cycles, but no xed-point DSP is designed that way. The new 24 bit xed-point DSP DAISY, which is able to execute the butter y in 4 cycles ev...

Orthogonal Frequency Division Multiplexing (OFDM) technology has been adopted by a variety of standards. This technology was chosen due to its robustness at high data rates in a frequency selective multipath channel. This paper describes a real-time implementation of a half-duplex OFDM system using Matlab software simulink, DSP processor TMS320C6713 and Code Composer Studio. In this approach, M...

We present SoftExplorer, a tool to estimate and analyze the power and energy consumption of an algorithm from the C program. The consumption of every loop is analyzed, and the influence of the data mapping is characterized. Several models of processor are available, from the simple RISC ARM7 to the very complex VLIW DSP TI-C67. Cache misses, pipeline stalls, and internal / external memory acces...

Unlike DSP compilation for high performance, research for low power optimisation has received little attention, although power dissipation is a critical issue for mobile devices. This paper presents an overview of power consumption models and power saving techniques for embedded DSP processors applications and evaluates their application to the Texas Instruments TMS320VC5510 Digital Signal Proc...

Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded DSP processor based on physical curr...

This paper examines architectural issues for a domain specific digital signal processor (DS-DSP) which is capable of fast decoding of block codes. In real time systems it was not possible before to employ common processors for this task because of a lack of architectural and arithmetical support. We proposed solutions for the arithmetical problem in previous work [6]. In this paper we focus on ...

The trend in programmable architectures for digital signal processing (DSP) is to move towards high-level language programming, which sets high requirements for compilers to efficiently exploit the instruction level parallelism in modern processors. In this paper, efficiency of transport triggered architectures (TTA) in DSP applications is discussed. The efficiency of a high-level compiler on a...

How to select an architecture which has better performance cost ratio, how to design a balanced architecture which can fit most DSP programs and how to generate a custom-fit DSP processor are important topics now. This paper presents a novel methodology based on source-level loop optimization which can avoid expensive retargetable compiler and simulator, and exhaustive experiments.

The paper presents two rapid control prototyping applications: velocity control of a DC motor and adaptive system identification and control of an automotive alternator. The control algorithms for the applications run on a TMS320F2812 DSP. Once the desired functionality has been captured and simulated, using MATLAB/Simulink/Embedded Target for Texas Instruments (TI) C2000 DSP environment can be...