business process improvement to a change in leadership. One hundred and eight respondents (32.2 percent) also pointed to planning as an important factor. Planning is included in the leadership group as it is most often a leadership initiative. Garland Elmore, associate vice president for teaching and learning information technology and dean of information technology at Indiana University, descr...

Considering fabrication variations, timing guardband is introduced to ensure design reliability. However, trade-off exists between guardband and design performance, especially the chip area discussed in this paper. To predict the variation of total chip area with guardband reduction, we construct the model from the basic Elmore delay theory and optimize the gate sizing and buffering to meet the...

We describe a \topology advisor" for routing of critical (multisource) buses in building-block design. The tool accepts as input a block layout, a two-layer routing cost structure superposed over the block layout, terminal locations for a multi-source bus, and source-sink delay upper bound (linear or Elmore delay) constraints for all terminal pairs. The b best routing solutions (b a user parame...

Delay of VLSI circuit components can be controlled by varying their sizes. In other words, performance of VLSI circuits can be optimized by changing the sizes of the circuit components. In this paper, we define a special type of geometric program called unary geometric program. We show that under the Elmore delay model, several commonly used formulations of the circuit component sizing problem ...

During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid bu ers to be inserted. They give restrictions on bu er locations. In this paper, we take these bu er location restrictions into consideration and solve the simultaneous maze routing and bu er insertion problem. Given a block placement de ning bu er location restriction...

The transmission behavior of interconnections in integrated circuits is often determined by their distributed RC effects. In this paper, we present a modeling technique, for incorporation in a layout-to-circuit extraction program, that accurately represents these effects. The method consists of first replacing IC interconnections by a complex RC network and then transforming this complex RC net...

In this paper, we present a fast algorithm for continuous wire-sizing under the distributed Elmore delay model. Our algorithm GWSA-C is an extension of the GWSA algorithm (for discrete wire-sizing) in CL93a]. GWSA-C is an iterative algorithm with guaranteed convergence to optimal wire-sizing solutions. When specialized to discrete wire-sizing problems, GWSA-C is an improved implementation of GW...

We first note that tests for interaction are missing in virtually all textbooks on nonparametric statistics. We will discuss some reasons why this is so. We then make a case for featuring tests for interaction in the course. By learning how to use median polish and graphical displays students can begin to conceptualize what an interaction means. This will strengthen their understanding of addit...

In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we present the Deferred-Merge Embedding (DME) algorithm, which in linear t...