The field of evolvable hardware has been fating a consistent problem since it’s inception, that the time taken to find an evolved solution is often limited because of time taken in the simulation of the hardware. We describe in this paper the rationale and design of an evolvable hardware (EHW) platform based on the use of a stand-alone processor (DSP) and a Field Programmable Transistor Array (...

In this work, we are developing a novel reconfigurable multiprocessor architecture, environment and tools for autonomous onboard processing in space platforms. Among the important features of our method are: reconfigurability and processor adaptability for high rate wireless functions; usage of system-on-chip (SOC) technology to embed hardware modules and reconfigurable blocks; integration of r...

We propose to develop reactive robot leg controllers in hardware using a morphogenetic approach that incorporates both evolutionary and developmental processes. Evolvable hardware has been crippled by issues of scalability and viability of evolved designs that arise when evolving complex circuits on modern mainstream field programmable gate arrays (FPGAs). To overcome these limitations requires...

Neural networks can recognize patterns very flexibly as humans do, even if inputs with noise or incompleteness are given. We aim at the implementation of this flexible mechanism for association by taking a completely different approach from neural networks. We name this approach “Evolvable Hardware” (EHW). EHW is a hardware device which can adapt its own hardware structure to the environment to...

This paper describes Multiple Interactive Outputs in a Single Tree (MIOST), a new form of Genetic Programming (GP). Our approach is based on two ideas. Firstly, we have taken inspiration from graph-GP representations. With this idea we decided to explore the possibility of representing programs as graphs with oriented links. Secondly, our individuals could have more than one output. This idea w...

During the past few years JPL has been actively involved in soft computing research encompassing theory, architecture, and electronic hardware applications. There are a host of soft computing applications that require orders of magnitude enhancement in speed compared to that obtained using simulations on digital machines. For on-board computing this is made possible by selecting suitable algori...

Mapping between genotype and phenotype using a model of biological development has been widely touted as a technique for evolving solutions to large, complex problems [1-3]. Here we describe two test-bed developmental systems for evolvable hardware problems, and compare each to a naive mapping system. We find that designing evolvable developmental systems is not a trivial problem, however early...

Evolvable hardware (EHW) refers to a selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). A lot of research has been done in this area several different EA have been introduced. Every time a specific EA is chosen for solving a particular problem, all its components, such as population size, initialization, selection mechanism, muta...

An indirect-mapping approach to evolvable algorithms is presented that is specifically intended for evolvable hardware. The conventional wisdom is that because hardware is configured by downloading a bitstream of a fixed size and hardware-specific format, hardware is not suited to genetic algorithms in which the size of the chromosome may vary. The algorithm presented herein departs from the tr...

The design productivity gap in the electronic industry is a well-known fact. How can the design community utilize the design capacity that technology is offering and at the same time ensure its correctness? To find solutions to the problem of developing large and complex designs new design paradigms are required (Semiconductor Industry Association, 1997). One possible solution is to turn away f...