A model has recently been developed that relates test coverage and defect coverage. It has been shown that this model can be used to estimate the residual defect density. Defect finding capability of sets of tests with different coverage values has recently been studied by Frankl and Iakounenko. They have defined measure test effectiveness, and have evaluated it for programs containing a single...

1 Currently affiliated with Intel Corporation ABSTRACT This paper presents the results for very detailed studies of pattern and timing-dependent failures from the 309 dies in the retest of an experimental test chip. 22 out of the 50 CUTs with pattern-dependent failures had test escapes if the test sets were reordered. Some timing-dependent failures became timing-independent combinational (TIC) ...

Test generation complexity varies exponentially as the depth of cycles in the S-graph of the circuit. We map the hard-to-reach states obtained from a sequential test generator onto the cycles in the S-graph of the circuit. We then proceed to rank the cycles in terms of the testability gain that would result if the cycle were broken. The primary objective is not to cut all the cycles but to cut ...

Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting/propagating these target faults. Adding scan to the circuit increases reachability of these hardto-reach and/or previously unreachable states. In this paper, we postulated that fewer scan ipops are needed to make these states reachable. The states necess...

|We propose a linear complexity method to estimate robust path delay fault coverage in digital circuits. We adopt a path counting scheme for a true-value simulator that uses ags for each signal line. These ags determine the new path delay faults detected by the simulated vector pair. Experimental results are presented to show the e ectiveness of the method in estimating path delay fault coverage.

The ASIC design flow is rapidly moving towards higher description levels, and most design activities are now performed at the RT-level. However, test-related activities are lacking behind this trend, mainly since effective fault models and test pattern generation tools are still missing. This paper proposes techniques for implementing a high-level ATPG. The proposed algorithm mixes a code cover...

Differential fault analysis (DFA) poses a significant threat to Advanced Encryption Standard (AES). Only a single faulty ciphertext is required for contemporary DFA to extract the secret key of AES using an average of 2 computations. Concurrent error detection (CED) is widely used to protect AES against DFA. Traditionally, these CEDs are evaluated with uniformly distributed faults, and the resu...

Self-checking circuits can detect the presence of both transient and permanent faults. A self-checking circuit consists of a functional circuit, which produced encoded output vectors, and a checker, which check the output vectors. A self-checking system consists of an interconnection of self-checking circuits. The advantage of such a system is that errors can be caught as soon as they occur; th...

Keerthi Heragu Michael L. Bushnell Vishwani D. Agrawal Dept. of Electrical & Computer Eng. Dept. of Electrical & Computer Eng. AT&T Bell Labs Rutgers University Rutgers University 600 Mountain Avenue Piscataway, NJ 08855-0909 Piscataway, NJ 08855-0909 Murray Hill, NJ 07974 [email protected] [email protected] [email protected] Abstract|We propose a linear complexity method to est...

A partial scan selection strategy is proposed in which flip-flops are selected via newly proposed dynamic reachability and observability measures such that the remaining hard-to-detect faults are easily detected. This is done by taking advantage of the information available when a target fault is aborted by the test generator. A partial scan selection tool, IDROPS, has been developed which sele...