Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional field-programmable gate arrays (FPGAs) since they efficiently reuse limited hardware resources in time. One of the typical DPGA architectures is a multi-context FPGA (MC-FPGA) that requires multiple memory bits per configuration bit to realize fast context switching. However, this additional memory...

This paper investigate the possibility and effectiveness of multi-mode vibration control of a plate through real-time FPGA (Field Programmable Gate Array) implementation. This type of embedded system offers true parallel and high throughput computation abilities. The control object is an aluminum panel, clamped to a Perspex box’s upper side. Two types of control laws are studied. The first belo...

An accumulator and cycling unit from the Electronic Numerical Integrator and Calculator (ENIAC) are implemented on a Field Programmable Gate Array (FPGA). The FPGA implementation is not architecturally identical to the original ENIAC, but the original architectural design is maintained where possible. The design maintains decimal number representation, ring counters to increment numbers, and te...

This paper presents an optimized digit-by-digit calculation method to solve complicated square root calculation in hardware, as a proposed simple algorithm for implementation in field programmable gate array (FPGA). The main principle of proposed method is two-bit shifting and subtracting-multiplexing operations, in order to achieve a simpler implementation and faster calculation. The proposed ...

This paper introduces a fast infrared spots detection algorithm designed for field-programmable gate array (FPGA) implementation. The proposed algorithm processes four pixels per clock cycle and detects infrared spots in a single pass over a frame. The implementation of the algorithm is only composed of combinatorial logic and registers. Furthermore, the execution time of the algorithm is indep...

Abstract—Space-Time Adaptive Processing (STAP) algorithm has recently been used in Passive Bi-static Radars (PBR) because it removes the clutter and non-cooperative transmitter effectively making the target detection easy in harsh environments like air-ground. Realtime implementation of STAP is a very challenging task as it is computationally-intensive, time-critical and resource-hungry process...

This paper presents a pipelined Adaptive Viterbi algorithm of rate 1⁄2 convolutional coding with a constraint length K = 3 which is designed in a reconfigurable hardware to take full advantage of algorithm parallelism, specialization and the throughput rate. In present work, the hardware implementation of the pipelined Adaptive Viterbi algorithm is performed using FPGA processor (Spartan-3AN st...

Field-programmable gate array (FPGA) technology represents a potential alternative to classical CPUs and GPUs in the post-Moore era from edge computing data centers [...]

This paper constructs fully parallel NN hardware realization of Artificial Neural Network (ANN) depends on the efficient execution of single neuron. Field Programmable Gate Array (FPGA) reconfigurable computing architecture is appropriated for hardware achievement of ANN. Numerous implementation of ANNs have been reported in scientific documents, trying to reduce Neural Networks NNs hardware ci...

The emphasis of this paper is on MicroBlaze implementation of GPS/INS integrated system on Virtex-6 field programmable gate array (FPGA). Issues related to accuracy of position, resource usage of FPGA in terms of slices, DSP48, block random access memory, computation time, latency and power consumption are presented. An improved design of a loosely coupled GPS/INS integrated system is described...