-In current scenario, VLSI circuit’s greatest challenges is to reduce the power dissipation and surface area so that longer life and high performance achieved to greater extent. The key parameter is threshold voltage to reduce the leakage power. In our proposal, we design low power and high performance JK flip-flop. JK flip-flop is designed with the help of D flip-flop and with some logic gates...

This paper describes an original circuit design of a static CMOS double-edge triggered flip-flop (DETFF). Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock frequency (as compared to a circuit with single-edge triggered...

-In many digital Very Large Scale Integration design, clock system is one of the most power consumption component. It consumes 30% to 60% of the total system power. As we are in need to reduce the power consumption on portable digital circuit because power budget is severely limited on portable digital circuit. To achieve this requirement, a clock system employing two techniques such as Dual Ed...

This paper describes a semi-dynamic CMOS flip-flop family featuring embedded Threshold Logic functions. First, we present the concept of flip-flop featuring embedded Threshold Logic, and then we describe the circuit and its operation. Subsequently, we present the design issues and the experimental results of such Threshold Logic flip-flops, obtained in 0.25pm CMOS technology. It is shown in thi...

Flip Flops are critical timing elements in digital systems which has large impact on circuit speed and power consumption. The performance of flip flop is an important parameter to determine performance of whole synchronous circuit. In this paper, comparison of existing flip flops with different parameters is calculated. A new design a low power pulse triggered flip-flop (FF) has been proposed h...

We present an optical shift register that consist out of two serially connected optical flip-flop memories driven by common clock pulses. Each optical flip-flop consists out of two ring lasers sharing a single active element, which makes the optical flip-flops easily cascade with each other. The two cascaded optical flip-flops are controlled by the clock pulses in such a way that the input data...

In Integrated Circuit industry power has become a major contribution. The main attribute is the clock power in circuits of VLSI. In today’s VLSI design scenario, power utilization by clocking takes up a vital role especially in design that uses deeply scaled CMOS technology. Proficient power utilization tends to be an important constraint in modern IC design. The underneath idea of multi bit fl...

Different flip-flop designs vary in the number and complexity of logic stages they contain, and hence have different inherent parasitic delays and output drive strengths. We examine the effect of electrical load on flip-flop delay and energy consumption and show that the relative ranking of optimized flip-flop structures varies widely with both electrical effort and absolute load. We also show ...

Quantum dot cellular automata (QCA) introduces a pioneer technology in nano scale computer architectures. Employing this technology is one of the solutions to decrease the size of circuits and reducing power dissipation. In this paper, two new optimized FlipFlops with reset input are proposed in quantum dot cellular automata technology. In addition, comparison with related works is performed.Th...

Flip-Flop_1: Firstly, the old flip-flop construction that we choose to implement is the classic single edge triggered flip-flop (SETFF) which is shown in FIGURE 10.24 in the book " CMOS VLSI Design A Circuits and Systems Perspective " 4th Edition. The figure is shown below. Fig A-1 Resettable Flip-Flop The schematic that we construct is shown as follows: Fig A-2 Resettable Flip-Flop Schematic T...