In previous work we have demonstrated how the functional language SAFL can be used as a behavioural hardware description language. Other work (such as μFP and Lava) has demonstrated that functional languages are apposite for structural hardware description. One of the strengths of systems such as VHDL and Verilog is their ability to mix structuraland behavioural-level primitives in a single spe...

This paper reports on some initial results in using LOTOS as a hardware description language. LOTOS, the Language Of Temporal Ordering Specifications, is a language that has been conceived in the framework of Open Systems Interconnection (OSI) standardization as a tool for the formal description of OSI services and protocols. We present some examples to show how LOTOS can be applied to the spec...

This paper describes a plan to integrate current digital hardware design technology into the computer science hardware curriculum. The project will approach digital hardware design from a perspective familiar to computer science students. Techniques featuring Object Oriented Design (OOD), Object Oriented Programming (OOP), code reuse, rapid prototyping, project centered learning, and visualizat...

This contribution reports on an approach to hardware/software codesign based on a state transition system design language MAD. MAD has been used for software design for some time, but is now being extended to hardware design by adding the hardware description language VHDL as one of its target languages. The experience of adding a new dimension (i.e. hardware) to the design space and of dealing...

Modern chips may contain a large number of embedded test, debugging, configuration, and monitoring features, called instruments. An instrument and its instrument access procedures may be pre-developed and reused, and each instrument—in different chips and through the life-time of a chip—may be accessed in different ways, which requires retargeting. To address reuse and retargeting of instrument...

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The coverification of a given HW/SW system consists of checking whether the implementation of the software and hardware parts and their integration fulfill or not some or all the specification requirements of this system. In the case of a distributed model, the SW and HW system blocks are described respectively by HLL (High Level Language) and HDL (Hardware Description Language) codes. When dea...

This tutorial describes how Altera's Quartus R II software deals with the timing issues in designs based on the Verilog hardware description language. It discusses the various timing parameters and explains how specific timing constraints may be set by the user.