The aim of this paper is FPGA implementation of architecture of floating point arithmetic core and analysis of area and timing performances of that arithmetic core. The basic concept behind designing such a core is to optimally utilize the algorithms of floating point arithmetic operations, i.e., addition, subtraction, multiplication and division and to enhance the operational speed of these ca...

In this paper, a new method is introduced for improving the efficiency of the Residue Number System, which uses both binary and residue representations in order to represent a number. A residue number system uses the remainder of the division in several different modules. Conversion of a number to smaller ones and carrying out parallel calculations on these numbers greatly increase the speed of...

This paper presents a low-power bit-serial Viterbi decoder chip with the coding rate r = 1=3 and the constraint length K = 9 (256 states). This chip has been implemented using 0.5 m three-layer metal CMOS technology and is targeted for high speed convolutional decoding for next generation wireless applications such as wide-band CDMA mobile systems and wireless ATM LANs. The chip is expected to ...

Abstract—Redundant Binary Signed Digit Adder and Multiplier circuits are logic circuits which are designed to perform high-speed arithmetic operations. Fast RBSD adder cell, proposed by Kal and Rajshekhar in 1990 was modified by Neelam Sharma in 2006 using universal logic. The proposed adder is re-modified for reducing the number of gates and thus the circuit complexity and cost. Further due to...

A comprehensive library of arithmetic units written in synthesizable VHDL code has been developed. The library contains components for a variety of arithmetic operations and for different speed requirements. The library components are implemented as circuit generators in parameterized structural VHDL code. Their modular and well-documented source code allows for simple usage and easy customizat...

In this paper, the implementation of residue number system reverse converters based on hybrid parallel prefix adders is analyzed. The parallel prefix adder provides high speed and reduced delay arithmetic operations but it is not widely used since it suffers from high power consumption. Hence, a hybrid parallel prefix adder component is presented to perform fast modulo addition in Residue Numbe...

This paper introduces a novel method for complex number representation. The proposed Redundant Complex Binary Number System (RCBNS) is developed by combining a Redundant Binary Number and a complex number in base (-1+j). Donald [1] and Walter Penny [2,3] represented complex numbers using base –j and (-1+j) in the classified algorithmic models. A Redundant Complex Binary Number System consists o...

Solving a super-high dimensional equations group is widely used in science and engineering, but the slow solution speed is the biggest problem researchers face. Research on FPGA based evolvable hardware chips for solving the super-high dimensional equations group (SHDESC) is proposed in this paper. These chips can be implemented on a milliongate scale FPGA chip. The core architecture of SHDESC ...

Curve based cryptography are preferred for embedded hardware since they require shorter operand size than RSA to attain the same security level. So ECC and HECC are more suitable in constrained environment such as smart cards if we can select suitable curves and efficient scalar multiplication technique to speed up arithmetic on the curve. With this in view, this paper explores in details the m...