In this paper we present a 1 bit Full Adder Cell. It was implemented with lesser number of transistors and lesser power consumption compared to the existing implementations of the Full Adder. Simulations are carried for supply voltages of 1.2v, 0.8v in HSPICE at 0.18μmCMOS technology. Proposed Full Adder results show that there was a reduction of power consumption and efficient in area. Area wa...

A new current-mode squaring circuit that can be used as a basic building block in analog signal processing systems is proposed. The design is based on MOS operating in the subthreshold region to assure low voltage and low power consumption. The performance of the design was confirmed by HSPICE simulation in 0.18m CMOS process. The circuit is operated by ±0.7V supply voltage and consumes 0.2μW ...

Utilizing memristor to obtain multi-level memory in nano-crossbar is a promising approach to enhance the memory density. In this paper, we proposed a solution for multi-level programming of memristor in nanocrossbar, which can be implemented on nanocrossbar without the need for extra selective devices. Meanwhile, using a general device model, this solution is demonstrated to be adaptive to a wi...

Present ferroelectric (FE) capacitor models mostly rely on continuous hysteresis loop characteristics of FE materials. Our experimental results show that this approach overestimates the remanent and saturation polarizations available for nonvolatile semiconductor memories by more than 50%. A behavioral transient model based on pulse measurement results is proposed and implemented as an HSPICE m...

This paper presents a high CMRR and wideband current feedback Instrumentation Amplifier (IA). The proposed IA architecture consists of Fully Balanced Differential Difference Amplifier (FBDDA) and Differential Difference Amplifier (DDA) based on 2 generation current conveyor (CCII) with a buffer. From the simulation results evaluated by HSPICE, the proposed IA exhibits average CMRR was 109.3 dB ...

This study presents a proposal to estimate the power consumption of the complex logic gate with topology dogbone transistors, which reduces the effects of radiation, by of the estimate of input and output capacitance of gate. The simulation tools have been implementation and SIS and comparator with the Hspice Synopsys. The first results show approximately an error of 5% between the proposed and...

We present a simple and accurate model to compute the power dissipated in sub-micron CMOS buffers driving RC interconnect lines. The expression obtained accounts for the main effects in current sub-micron CMOS technologies as carrier velocity saturation effects, input-output coupling capacitor, output load, input slew time, device sizes and interconnect resistance. Results are compared to HSPIC...

The pixel bootstrapping method is successful to be applied to implement the dot inversion without addition complex controls in LCoS with frame buffer pixels. The relations of common voltage modulation method and bootstrapping method are analyzed. The dot inversion in frame-by-frame addressing method is explained. The dot inversion and the data voltage loss compensation are implemented by bootst...

Articulatory patterns of the lateral approximant /1/, both dark and light allophones, in American English were analyzed through magnetic resonance imaging (MRI) and electropalatography (EPG). Vocal tract lengths, area functions, and cavity volumes, were measured from the MR images, while EPG data were used for studying interand intra-speaker variabilities in lingua-palatal contact patterns. Aco...

Electricalcircuit Yes Yes Medium (12% error predicting cell voltage and thermal characteristics , 5% error predicting cycle aging) medium Medium (>15 parameters) Medium Electricalcircuit Yes No Medium Medium High (>30 parameters) Medium Thermostati c charge method: high Discretetime Yes No Medium (1% compared to Hspice continuous-ti me model) Medium Medium (>15 parameters) Medium Dynamic Power ...