Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation.

This paper presents a BIST architecture, based on a single micro-programmable BIST Processor and a set of memory Wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing.

Article history: Received 29 June 2010 Received in revised form 18 October 2012 Accepted 18 October 2012 Available online 20 November 2012 0045-7906/$ see front matter 2012 Elsevier Ltd http://dx.doi.org/10.1016/j.compeleceng.2012.10.00 q Reviews processed and approved for publication ⇑ Corresponding author. Tel.: +3

Single Input Change (SIC) testing has been proposed for robust path delay fault testing. In this letter a new Built-In Self Test (BIST) method for SIC vector generation is presented. The proposed method compares favourably to the previously proposed methods for SIC pattern generation with respect to hardware overhead and time required for completion of the test.

Logic built-in self-test (LBIST), is a mechanism that lets an (IC) test the integrity of its own digital logic structures. LBIST operates by stimulating the logic-based operations of the IC and then detecting if the logic behaved as intended. The main advantage of LBIST is that it provides test capability without an external tester. In particular, safety-critical designs need to be tested and r...