In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based field programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the perf...

A structured light system using a digital video projector is widely used for 3D shape measurement. However, the nonlinear gamma of the projector causes the projected fringe patterns to be nonsinusoidal, which results in phase error and therefore measurement error. It has been shown that, by using a small look-up table (LUT), this type of phase error can be reduced significantly for a three-step...

Field programmable gate arrays (FPGAs) have become an attractive implementation medium for digital circuits. FPGA design’s big challenge is to find a good trade-off between flexibility and performance in terms of power dissipation, area density, and delay. This paper presents a new cluster-based FPGA architecture combining mesh and hierarchical interconnect topologies. Based on experimental met...

Underwater acoustic communication module based on Orthogonal Frequency Division Multiplexing (OFDM) uses rate 1⁄2 convolutional encoders and Turbo decoders for error control coding. Turbo decoders are designed with two Viterbi decoders that operate in sequence to improve Log Likelihood Ratio (LLR). The computation complexity of Viterbi decoders limits their use for high speed decoding as the de...

In this paper an efficient design and implementation of ITU-R BT.601 video filter has been presented for digital television receivers. The proposed video filter has been realized using MAC algorithm. The implementation is based on efficient utilization of embedded multipliers and look up table (LUT) of the target device to improve speed, area efficiency and power consumption. It is an efficient...

In arithmetic circuits for digital signal processing, radixes other than two are often used to make circuits faster. In such cases, radix converters are necessary. However, in general, radix converters tend to be complex. This paper considers design methods for p-nary to binary converters. First, it considers Look-Up Table (LUT) cascade realizations. Then, it introduces a new design technique c...

There are two main approaches to the problem of gender classification, Support Vector Machines (SVMs) and Adaboost learning methods, of which SVMs are better in correct rate but are more computation intensive while Adaboost ones are much faster with slightly worse performance. For possible real-time applications the Adaboost method seems a better choice. However, the existing Adaboost algorithm...

This paper proposes a pipelined non-deterministic finite automaton (NFA)-based string matching scheme using field programmable gate array (FPGA) implementation. The characteristics of the NFA such as shared common prefixes and no failure transitions are considered in the proposed scheme. In the implementation of the automaton-based string matching using an FPGA, each state transition is impleme...